Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2006-07-24
2010-02-23
Clark, Sheila V. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S686000
Reexamination Certificate
active
07667308
ABSTRACT:
A semiconductor package includes a leadframe. An upper lead is disposed above the leadframe. A first die is attached to a lower surface of the upper lead to provide electrical conductivity from the first die to the upper lead. A second die is attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having an upper lead, lower lead, and an elevated die paddle. A first die, attached to a plurality of dies in a wafer form, is attached to a second die. The first die is singulated from the plurality of dies. The first and second dies are attached to the elevated die paddle structure. The first die is wire bonded to the lower lead. An encapsulant is formed over the first and second dies. The elevated die paddle is removed to expose a surface of the upper lead and second die.
REFERENCES:
patent: 7151013 (2006-12-01), Corisis et al.
patent: 7384819 (2008-06-01), Yip et al.
patent: 2005/0194676 (2005-09-01), Fukuda et al.
patent: 2006/0102989 (2006-05-01), Lee et al.
patent: 2006/0261453 (2006-11-01), Lee et al.
Chow Seng Guan
Do Byung Tai
Kuan Francis Heap Hoe
Atkins Robert D.
Clark Sheila V.
STATS ChipPAC Ltd.
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