Large-scale trimming for ultra-narrow gates

Details Large-scale trimming for ultra-narrow gates Large-scale trimming for ultra-narrow gates

2006-03-07

2006-03-07

Tran, Mai-Huong (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C430S316000, C430S030000, C430S311000, C430S313000, C430S317000, C430S329000, C438S714000, C438S725000

Reexamination Certificate

active

07008866

ABSTRACT:
Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

REFERENCES:
patent: 6864041 (2005-03-01), Brown et al.

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