Metal fusion bonding – Process – Bonding nonmetals with metallic filler
Reexamination Certificate
1999-08-16
2001-10-09
Dunn, Tom (Department: 1725)
Metal fusion bonding
Process
Bonding nonmetals with metallic filler
C228S248100, C228S256000, C156S182000, C156S290000, C156S306300
Reexamination Certificate
active
06299053
ABSTRACT:
BACKGROUND OF THE INVENTION
A major problem facing manufacturers of wiring substrates, such as printed wiring boards (“PWBs”), chip carriers, and VLSI substrates, is the management of thermal expansion stresses between the materials of the substrate, in the case of a laminated substrate, and between the materials of the substrate and components mounted on the substrate.
Thermal stresses can arise in at least two situations. One situation is when a thermal gradient is present. A higher temperature in one area of the substrate, such as underneath a heat source, can cause thermal expansion relative to a cooler area of the substrate, even if the substrate is made of a single material. The effects of this situation can often be mitigated by slowly changing temperature, thus lowering the thermal gradient.
A second situation is when materials with different coefficients of thermal expansion (“CTE”) are used. One material then expands and contracts at a different rate (typically expressed as a dimensionless coefficient, e.g. mm/mm, per degree of temperature) than the other as the temperature changes. Differential CTEs can cause problems regardless of the rate at which the materials are heated or cooled. If the materials are bonded or otherwise attached together, thermal stress is generated when the temperature changes. This stress can result in deformation (warping) or even fracture of the material, in order to relieve the stress.
For example, PWBs are typically formed by laminating several layers of different materials together. Conductive layers, such as copper layers patterned according to a desired wiring layout, are typically separated by, and laminated to, dielectric layers that provide electrical insulation between the conductive layers. The dielectric layers are typically polymeric resins, such as epoxy resins. The dielectric layers often have a CTE of about 50-70 ppm/° C. while the metals used in the conductive layers have a CTE of about 16-17 ppm/° C. Thus, a heat source placed on a PWB or similar wiring substrate can create thermal stress.
The increased complexity of contemporary integrated circuits affects the problems arising from thermal stress in many ways. First, the high device count on very-large-scale integrated circuit (VLSI”) chips often means a single chip will generate more heat compared to a chip with a lower device count. The shrinking dimensions of the devices on the chips mean that the heat is often concentrated in a smaller area. Some ICs generate over 10 W/cm
2
. The shrinking dimensions also mean that the traces on the chip are finer pitch and the contact pads on the chip also have finer pitch, not to mention that the number of contact pads has substantially increased. Finally, the overall dimensions of VLSI chips have increased in many cases. The increased dimensions result in a greater total expansion or contraction, which can lead to higher thermal stress.
A variety of technologies have been developed to address the finer contact pitch and increased number of contacts. Examples include ball-grid arrays (“BGAs”), which are packaged chips with an array of bumps, typically solder dots, on one surface of the package. The package may include a chip carrier or lead frame, with the actual semiconductor chip bonded to the carrier and the electrical contacts brought from the IC chip to the balls of the BGA. Another example are known as “flip chips”, which are similar to BGA packages in that bumps, typically of solder, eutectic, or conductive adhesive, are formed over contact pads on the IC chip. The chip is then “flipped” onto a wiring substrate and bonded. Flip-chip is usually reserved to describe a type of direct chip attach, even though it is very similar to packaged BGA process.
Unfortunately, the IC package or flip chip may be made of a material, such as plastic, ceramic, or semiconductor, with a different CTE than any of the materials in the wiring substrate. To complicate matters, the finer pitch of the contact array typically means a finer wiring pattern must be used on the wiring substrate. The finer wires are not as strong as wider wires would be, and thus are more susceptible to breakage when subjected to stress. Similarly, if a shear stress develops between the IC and the substrate, a smaller solder ball will have less strength to resist the stress (including work hardening), and may fail at the joint, or may crack. A particularly insidious aspect of such failures is that an electrical contact may be established at one temperature, and not at another, as thermal expansion and contraction brings the cracked or broken halves of the electrical path together and apart.
Therefore, it is desirable to reduce the failures caused by thermal stress in wiring substrates and in assemblies of integrated circuits and wiring substrates.
SUMMARY OF THE INVENTION
The present invention provides a wiring substrate with reduced thermal expansion. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void extends a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. Wiring substrates according to the present invention include laminated PWBs, thin film circuits, lead frames, or chip carriers and can accept an integrated circuit, such as a die, a flip chip, or a BGA package.
In a specific embodiment, the wiring substrate is a laminated printed wiring board with the thermal stress reduction insert or void in a layer proximate to an outer layer to which the integrated circuit is joined (mounted). In a further embodiment the thermal stress reduction insert is an elastomer, such as a siloxane. In an alternative embodiment, the wiring substrate is a thin film substrate
In another embodiment, a constructive void is formed by filling a cutout portion of the inner layer with a material that thermally degrades when the laminate is processed.
In yet another embodiment, the layers of the laminate are pressed in selected regions, so that the layers in the thermal expansion stress region are not bonded.
These and other embodiments of the present invention, as well as its advantages and features, are described in more detail in conjunction with the text below and attached figures.
REFERENCES:
patent: 4313995 (1982-02-01), Delgadillo
patent: 4654248 (1987-03-01), Mohammed
patent: 4806195 (1989-02-01), Namysl
patent: 5153384 (1992-10-01), Iijima et al.
patent: 5326671 (1994-07-01), Brown et al.
patent: 5374344 (1994-12-01), Gall et al.
patent: 5688350 (1997-11-01), Hamilton et al.
patent: 5719749 (1998-02-01), Stopperan
patent: 5727310 (1998-03-01), Casson et al.
patent: 5804771 (1998-09-01), McMahon et al.
patent: 6121553 (2000-09-01), Shinada et al.
patent: 6175158 (2001-01-01), Degani et al.
patent: 0 044 247 A1 (1982-01-01), None
patent: 0 064 854 A1 (1982-11-01), None
patent: 0 260 857 A2 (1988-03-01), None
patent: 0 605 090 A1 (1994-07-01), None
patent: WO 89/09534 (1989-10-01), None
Beilin et al. (Derwent 2000-246607) Jul. 2000.*
Beilin et al. (Derwent 2000-246620) Jul. 2000.
Beilin Solomon I.
Chazan David
Kamath Sundar
Strandberg Jan I.
Dunn Tom
Kulicke & Soffa Holdings, Inc.
Stoner Kiley
Townsend and Townsend / and Crew LLP
LandOfFree
Isolated flip chip or BGA to minimize interconnect stress... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Isolated flip chip or BGA to minimize interconnect stress..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isolated flip chip or BGA to minimize interconnect stress... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2612960