Interconnect junction providing reduced current crowding and...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S618000, C257S773000

Reexamination Certificate

active

10878708

ABSTRACT:
Disclosed herein are a junction where electrical interconnects on a semiconductor substrate intersect and a method of manufacturing a junction where electrical interconnects on a semiconductor substrate intersect is disclosed. In one embodiment, the junction includes a portion of at least one current providing electrical interconnect having a length parallel to a longitudinal axis thereof and configured to provide a flow of electrical current. In addition, the junction includes a portion of at least one current receiving electrical interconnect having a length parallel to a longitudinal axis thereof and configured to intersect with the at least one current providing interconnect at the junction in order to receive the flow of electrical current from the at least one current providing interconnect. Also, in such an embodiment, the junction includes at least one current directing feature positioned between the current providing and current receiving interconnects, and oriented substantially non-perpendicular to the longitudinal axis of the at least one current providing interconnect.

REFERENCES:
patent: 5371411 (1994-12-01), Hara et al.
patent: 5539257 (1996-07-01), Hara et al.
patent: 5552639 (1996-09-01), Hara et al.
patent: 5633198 (1997-05-01), Lur et al.
S. Wolf and R.N. Tauber, Silicon Processing for the VSLI Era, vol. 1, Second Edition, Lattice Press, 2000, pp. 791-793.

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