Interconnect for low temperature chip attachment

Details Interconnect for low temperature chip attachment Interconnect for low temperature chip attachment

1996-09-25

2000-10-03

Arroyo, Teresa M.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

257737, 257779, H01L 2348, H01L 2352, H01L 2940

Patent

active

061277355

ABSTRACT:
A method of forming interconnects on an electronic device that can be bonded to another electronic device at a low processing temperature can be carried out by depositing a first interconnect material on the electronic device forming protrusions and then depositing a second interconnect material to at least partially cover the protrusions, wherein the second interconnect material has a lower flow temperature than the first interconnect material. The method is carried out by flowing a molten solder into a mold having microcavities to fill the cavities and then allowed to solidify. The mold is then aligned with a silicon wafer containing chips deposited with high melting temperatures solder bumps such that each microcavity of the mold is aligned with each high melting temperature solder bump on the chip. The aligned mold/wafer assembly is then passed through a reflow furnace to effect the transfer of the low melting temperature solder in the mold cavities onto the tip of the high melting temperature solder bumps on the wafer. A dual metallurgical composition bump is thereby formed by the two different solder alloys.

REFERENCES:
patent: 3512051 (1970-05-01), Noll
patent: 5508561 (1996-04-01), Tago et al.
patent: 5611884 (1997-03-01), Bearinger et al.

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