Integration of strained Ge into advanced CMOS technology

Details Integration of strained Ge into advanced CMOS technology Integration of strained Ge into advanced CMOS technology

2008-06-17

2008-06-17

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21092

Reexamination Certificate

active

07387925

ABSTRACT:
A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

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