Integrated self-aligned butt contact process flow and structure

Details Integrated self-aligned butt contact process flow and structure Integrated self-aligned butt contact process flow and structure

1997-07-28

1998-12-01

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438296, 438586, H01L 218244

Patent

active

058438165

ABSTRACT:
A method of forming a contact between a conductor and a substrate region in a MOSFET device is provided starting with forming a semiconductor substrate with a silicon oxide layer formed on the surface thereof. Then form a stack of a conductor material upon the surface of the silicon oxide layer and form a first dielectric layer upon the conductor material. Pattern the conductor stack into conductors. Form a butted contact pattern in the first dielectric layer by removal of the dielectric layer in at least one butted contact region. Form doped regions in the substrate self-aligned with the conductors. Form an etch stop layer over the device. Form a second dielectric layer over the device and pattern the second dielectric layer with contact openings therethrough down to the substrate and to the butted contact region. Employ the etch stop layer when patterning the second dielectric layer. Remove exposed portions of the etch stop layer subsequent to patterning the second dielectric layer. Form contacts to the substrate and the butted contact regions on the conductor through the contact openings.

REFERENCES:
patent: 5290728 (1994-03-01), Sato
patent: 5330929 (1994-07-01), Pfiester
patent: 5394358 (1995-02-01), Huang
patent: 5521113 (1996-05-01), Hsue et al.
patent: 5580806 (1996-12-01), Chang et al.
patent: 5681778 (1997-10-01), Manning
patent: 5731241 (1998-03-01), Jang et al.

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