Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-08-13
2003-09-09
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189070, C365S230060
Reexamination Certificate
active
06618303
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit for testing integrated circuits on a wafer using a test apparatus, a test structure and a method for this purpose. In particular, the invention relates to a method for testing integrated circuits on a wafer.
During their manufacture, semiconductor chips are subjected to a plurality of test methods. The test methods are essentially distinguished by front-end test methods and back-end test methods. The essential difference between the two separate test procedures is that, in the case of front-end test methods, the tests are carried out while the integrated circuits are still unseparated from the wafer, i.e. the wafer has not yet been sawn up into individual chips. In the case of back-end test methods, the individual chips are actually tested separately. The task of the front-end test method is, among other things, to carry out a first operational test for the integrated circuits on the wafer and to find faults. Some of the faults can be eliminated by a subsequent laser process by severing “hard fuses”, that is to say special fuses, using a laser and thereby replacing the faulty circuit regions with redundant circuits already provided on the chip. Such a laser process, also called laser trimming, needs to be carried out before the integrated circuits on the wafer are cut up into chips, because aligning individual chips in the laser apparatus creates considerable difficulties and would thus be very time-consuming and cost-intensive. By contrast, severing the hard fuses in an integrated circuit on the wafer that has not been sawn up is comparatively easy to do. For this reason, it is necessary to find out in the actual front-end test method which hard fuses mounted on the respective integrated circuit need to be severed in the subsequent laser process.
Particularly where reference voltages are produced internally in the chip, the manufacturing process results in fluctuations in the reference voltage produced from chip to chip. The fluctuations become particularly noticeable in the case of analog voltages because these small discrepancies from the reference value can have considerable effects on the operation of the circuit. Analog reference voltages can therefore move only within a certain tolerance range or need to be suited to the operation of the entire component. Whereas, previously, integrated circuits in which the reference voltage differed from the required voltage by more than a particular percentage were regarded as rejects, practice has now been changed to making the reference voltage settable on the respective chip, in order thus to obtain a virtually identical functionality for each individual chip. The setting of the reference voltage is effected using the laser trimming process described above.
The previous method of applying such a reference voltage externally during the operational tests to the circuit to be tested has the drawback that, between the externally applied voltage source and the contact on the integrated circuit, a voltage drop occurs which cannot be foreseen on account of the unknown currents which flow. Since, however, it is desirable to test the integrated circuits under the conditions of their later operation as far as possible, to which end the analog reference voltage potentials need to be applied appropriately inside the integrated circuit during testing, it is advantageous for the reference voltage to be provided internally in the chip for the actual front-end testing.
This now requires that the integrated circuit be set individually in the actual front-end test method, i.e. it is necessary to find out which of the hard fuses in an integrated circuit are severed in the later laser trimming process, and which are not. However, for reasons of throughput, conventional front-end test apparatuses always test a plurality of integrated circuits on a wafer at the same time and, in this context, supply each of the circuits with the same test pattern.
The test procedure first establishes which of the hard fuses need to be severed for the optimum setting in a subsequent laser process. Next, “soft fuses” are set. The soft fuses are memory cells that simulate the operation of the hard fuses during the test procedure in the integrated circuit. The settings then start the actual test method. In conventional test apparatuses, such setting of the soft fuses respectively affects all of a test run's integrated circuits connected in parallel. Individual setting is not possible, because the individual circuits cannot be addressed separately from one another by the test apparatus. However, it is usually possible for supply voltages supplying the individual integrated circuits to be turned on individually in conventional test apparatuses. Since the amount of time required for testing a chip is relatively great (approximately 30 minutes), it is not feasible, for reasons of economic viability, to set and test the chips successively.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit, a test structure and a method for testing integrated circuits which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which it is possible, before a parallel operational test for a plurality of integrated circuits on a wafer, to be able to make individual settings for parameters in the circuits to be tested.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit containing memory cells for storing test parameters; and an electronic circuit for carrying out an operational test and connected to the memory cells. The electronic circuit applies an operating signal and permits a single write operation to the memory cells and prevents any further writing to the memory cells.
The invention provides a circuit that has an electronic circuit as an aid to carrying out an operational test. The operational test is carried out by a test apparatus. Connected to the test apparatus are a plurality of integrated circuits which are supplied with test patterns in parallel and whose supply voltages can be applied individually by the test apparatus. The integrated circuit contains memory cells, for storing test parameters, which can have information written to them by the test apparatus and on which the operation of the respective integrated circuits depends. To prevent the memory cells in the connected integrated circuits from each receiving the same content, the invention provides that, once an operating signal, preferably a supply voltage, has been applied to the integrated circuit by the circuit, a single write operation to the memory cells is permitted, and thereafter further writing to the memory cells is prevented. This makes it possible for the integrated circuits to be successively provided with their individual settings as a result of writing to memory cells, without memory cells which have already had information written to them being overwritten.
The invention also provides a test structure having a test apparatus to which a plurality of such integrated circuits are connected. The test apparatus is able to turn the supply voltages for the integrated circuits on and off individually, which allows an individual response from the individual integrated circuits as a result of applied test patterns.
The inventive method involves ascertaining the parameters to be set in a preliminary test after the supply voltage to a first integrated circuit has been turned on. On the basis of the parameters obtained, memory cells in the first integrated circuit have information written to them. After that, the supply voltage is applied to a next integrated circuit, a preliminary test is carried out, and memory cells have information written to them on the basis of the parameters obtained. This is carried out until the parameters have been set for all the connected integrated circuits. Next, the actual operational test is then carried out by the test apparatus for
Gruber Arndt
Ruf Bernhard
Schneider Ralf
Wirth Norbert
Dinh Son T.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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