Integrated circuit comprising a test mode secured by the use...

Details Integrated circuit comprising a test mode secured by the use... Integrated circuit comprising a test mode secured by the use...

2011-04-05

2011-04-05

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000

Reexamination Certificate

active

07921342

ABSTRACT:
An electronic circuit includes configurable cells capable of being functionally linked to logic cells with which they cooperate to form at least one logic circuit if a chaining command signal is in a first (inactive) state. The electronic circuit also includes a logic interconnection circuit for performing the following functions if the chaining command signal is in a second (active) state. Functionally connecting the configurable cells in a linear feedback shift register if an authentication signal is in a first state, or functionally connecting the configurable cells in a chain in a predefined order to form a shift register if the authentication signal is in a second state.

REFERENCES:
patent: 5574733 (1996-11-01), Kim
patent: 5708715 (1998-01-01), Vicard
patent: 6158033 (2000-12-01), Wagner et al.
patent: 6294816 (2001-09-01), Baukus et al.
patent: 6457145 (2002-09-01), Holmberg et al.
patent: 6611929 (2003-08-01), Barnes
patent: 7106091 (2006-09-01), Gammel
patent: 7178039 (2007-02-01), Mueller
patent: 7725786 (2010-05-01), Bancel et al.
patent: 2007/0005993 (2007-01-01), Jacobs
patent: 2008/0148118 (2008-06-01), Morgan et al.
patent: 196152 (1986-10-01), None
“Dynamically configurable security for SRAM FPGA bitstreams” by Bossuet et al. This paper appears in: Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International Publication Date: Apr. 26-30, 2004.
“High-Performance Software Protection Using Reconfigurable Architectures” by Zambreno et al. This paper appears in: Proceedings of the IEEE Publication Date: Feb. 2006 vol. 94, Issue: 2 on pp. 419-431.
“Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration” by Yohei Hori et al. This paper appears in: Field Programmable Logic and Applications, 2006. FPL '06. International Conference on Publication Date: Aug. 2006 on pp. 1-4.

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