Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-12-11
2007-12-11
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C713S194000
Reexamination Certificate
active
11046381
ABSTRACT:
An electronic circuit, having a test mode in application of the “internal scan path” technique, includes a plurality of configurable cells and a control circuit. The electronic circuit is adapted to working in a standard mode of operation or in a test mode during which the control circuit is active and configures the configurable cells either in a functional state or in a chained state. The electronic circuit furthermore includes a validation circuit that performs the following operations successively when it receives an instruction for changing the mode of operation (TEST, FIN) of the electronic circuit: produce initialization signals (INIT1, INIT2, . . . , INITN) to command the initialization of all the configurable cells, and then produce a mode-changing signal (VAL).
REFERENCES:
patent: 5293610 (1994-03-01), Schwarz
patent: 5452355 (1995-09-01), Coli
patent: 6457126 (2002-09-01), Nakamura et al.
patent: 7076667 (2006-07-01), Gama et al.
patent: 2002/0133773 (2002-09-01), Richter et al.
patent: 2003/0204801 (2003-10-01), Tkacik et al.
patent: 1089083 (2001-04-01), None
Scan Based Side Channel Attack on Dedicated hardware implementations of Data Encryption Standard' by Yang et al. International Test Conference, Proceedings. ITC 2004. Publication Date: Oct. 26-28, 2004 pp. 339-344 ISBN: 0-7803-8580-2 INSPEC Accession No. 8291736.
“Automatic Test Equipment (ATE) on a Network (securing access to equipment and data)” by McCarty, AUTOTESTCON Proceedings, 2000 IEEE Publication Date: 2000 On pp. 490-496 ISBN: 0-7803-5868-6 INSPEC Accession No. 6812928.
Jaramillo, K., et al., “10 Tips for Successful Scan Design: Part One,” EDN Electrical Design News, Cahners Publishing Co., Newton, MA, US, vol. 45, No. 4, Feb. 17, 2000, pp. 67-73, 75, XP000966353, ISSN: 0012-7515.
Search Report for French Patent Application No. 0400835 dated Oct. 4, 2004.
Bancel Frédéric
Hely David
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
Gutman Jose
LandOfFree
Integrated circuit comprising a test mode secured by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit comprising a test mode secured by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit comprising a test mode secured by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3840527