Insulator for integrated circuits and process

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Reexamination Certificate

active

06559046

ABSTRACT:

TECHNICAL FIELD
The present invention is concerned with the use of certain flowable oxide layers as back end insulators for semiconductor devices. The present invention provides an insulator that exhibits a unique combination of relatively low dielectric constant below 3.2 and excellent gap fill capability. The back end insulator of the present invention can be formed by curing a flowable oxide layer and by annealing in the presence of hydrogen and aluminum.
The present invention is also concerned with the use of certain flowable oxides as an insulator between devices, that is, to electrically isolate the devices from each other. The isolator for this purpose can be formed by curing a flowable oxide and by annealing in the presence of hydrogen with or without aluminum.
BACKGROUND ART
The use of thin film ceramic silica coatings as protective and dielectric layers for electronic devices is known in the art. Currently, SiO
2
is used as the back-end dielectric in semiconductor devices. However, as chip function integration increases, back end wiring densities also increase. Because of this, there exists a greater need for intra-level insulators having lower dielectric constants than the presently used SiO
2
. This is crucial in order to reduce delays due to cross-talk and stray capacitance. Presently used SiO
2
has a dielectric constant of 4, which may limit its use because of the potential cross-talk and RC delays.
Moreover, because of reduced spacings between lines, the need for the insulation to conformally fill small spaces is increasingly important.
Since device density is also increasing with increasing complexity, the need to electrically insulate devices from each other has become important as well. With smaller inter-device dimensions, providing trenches conformally filled with dielectrics between devices, will become increasingly difficult.
SUMMARY OF INVENTION
The present invention provides an insulator that exhibits a unique combination of low dielectric constant below 3.2 and excellent gap fill capability. For example, insulators, according to the present invention, exhibit excellent gap-fill for an aspect ratio of 3 with depths of 400 nm or less.
In particular, the present invention is concerned with an insulator for covering an interconnection wiring level in a surface thereof on a semiconductor substrate containing semiconductor devices comprising:
a first flowable oxide layer coated on the interconnection wiring level, wherein said layer is cured. The layer is also annealed in the presence of hydrogen and aluminum. The hydrogen diffuses into the flowable oxide layer and reduces its dielectric constant to a value below 3.2.
The present invention is also concerned with an insulation for covering an interconnection wiring level in a surface thereof on a semiconductor substrate containing semiconductor devices comprising a cured hydrogen silsesquioxane polymer having a dielectric constant of below 3.2 and being passivated by externally introduced hydrogen.
The present invention is also concerned with a process for covering an interconnection wiring level in a surface thereof on semiconductor substrate which comprises:
coating a first flowable oxide layer onto the interconnection wiring level;
curing the flowable oxide layer, and annealing said layer wherein said annealing is carried out in the presence of hydrogen and aluminum to cause gas to diffuse into the flowable oxide layer and reduce its dielectric constant to a value below 3.2.
The present invention is also concerned with using the flowable oxide as a dielectric to electrically insulate neighboring devices. The structure comprises:
two neighboring or adjacent FET or bipolar transistor devices;
a trench in the substrate located between these devices; and
wherein the trench is filled with the flowable oxide that has been cured and annealed.
According to this aspect of the present invention, the flowable oxide is annealed in the presence of hydrogen and either in the presence or absence of aluminum.
The present invention is also concerned with a process for insulating adjacent devices in a semiconductor substrate. The process comprises providing a semiconductor device comprising a semiconductor substrate; at least two FET or bipolar transistor devices and a trench in the substrate located between the devices. The process further includes flowing a flowable oxide into the trench followed by curing and annealing. The annealing is carried out in the presence of hydrogen.


REFERENCES:
patent: 4239346 (1980-12-01), Lloyd
patent: 4349609 (1982-09-01), Takeda et al.
patent: 4576834 (1986-03-01), Sobczak
patent: 4756977 (1988-07-01), Haluska et al.
patent: 4849296 (1989-07-01), Haluska et al.
patent: 5059448 (1991-10-01), Chandra et al.
patent: 5085893 (1992-02-01), Weiss et al.
patent: 5118530 (1992-06-01), Hanneman et al.
patent: 5194928 (1993-03-01), Cronin et al.
patent: 5258334 (1993-11-01), Lantz, II
patent: 5319247 (1994-06-01), Matsuura
patent: 5320868 (1994-06-01), Ballance et al.
patent: 5370903 (1994-12-01), Minz et al.
patent: 5370904 (1994-12-01), Minz et al.
patent: 5380555 (1995-01-01), Minz et al.
patent: 5387480 (1995-02-01), Haluska et al.
patent: 5441765 (1995-08-01), Ballance et al.
patent: 5457073 (1995-10-01), Ouellet
patent: 5496776 (1996-03-01), Chien et al.
patent: 5516721 (1996-05-01), Galli et al.
patent: 5523163 (1996-06-01), Ballance et al.
patent: 6-196574 (1994-07-01), None
Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, 1990, pp. 188-191.*
Wolf et al., Silicon Processing for the VLSI Era, vol. 1, Process Technology, Lattice Press, Sunset Beach, CA, pp. 220-223.
Pramanik et al., “Reliability of Multilevel Circuits Using Hydrogen Silsesquioxane FOxfor Interlevel Dielectric Planarization,” Jun. 8-9, 1993 VMIC Conference, 1993 ISMIC-102/93/0329, pp. 329-331.
Ballance et al., “Low Temperature Reflow Planarization Using a Novel Spin-on Interlevel Dielectric,” Dow Corning Corporation, Fremont, CA, VMIC Conference, Jun. 9, 1992.

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