Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-10-24
2002-08-27
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S051000
Reexamination Certificate
active
06441396
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to the field of semiconductor device formation, and more specifically to a method and apparatus, integrated with said devices, for measuring mechanical stress induced in those devices. Such stress is either induced by the intrinsic fabrication process of the devices, or by extrinsic means, such as a vacuum chuck used during electrical tests. The method is particularly useful for measuring mechanical stress on semiconductor devices induced by the process of formation of either dielectric-filled isolation trenches or by semi-recessed oxide (SROX) isolation regions, which abut the devices of interest. The process of forming such isolation regions is well known in the art to be a significant source of stress.
2. Related Art
Dielectric-filled trench isolation is a common method of electrically isolating solid state silicon devices. It is especially common in complementary metal-oxide semiconductor (“CMOS”) technology as an alternative to back-biased isolation diffusion techniques used in negative-channel metal-oxide semiconductor (“NMOS”), positive-channel metal-oxide semiconductor (“PMOS”), or bipolar technologies. However, dielectric-filled trench isolation is difficult to implement in CMOS technology.
There are two significant drawbacks to the use of dielectric-filled trench isolation. First, the oxidation of the etched trench, which induces generally compressive stresses into the laterally adjacent silicon. Second, there is a densification of the dielectric that is deposited to fill the trench, and this densification induces tensile stress into the adjacent silicon. Thus, at the conclusion of the isolation trench construction process, the stress induced in the silicon is both compressive close to the surface, and tensile deeper down. These resulting stresses effect both device defects and device parameters.
Certain aspects of trench isolation as used in semiconductor structures causes the semiconductor structure to behave much the same as a piezoresistive device (i.e., a device whose resistance changes with the applied stress), and the effects of induced mechanical stress can modulate the nominal electrical behavior of a properly designed device, or array of such devices, for the purpose of measuring the induced stress. It is to be noted that extrinsically generated stress will also modulate device behavior and that this stress, too, can effectively be measured.
Devices known in the related art are designed to measure stress under controlled conditions, and are not meant to measure the process-induced stresses which are an accidental by-product of very large-scale integration (“VLSI”) fabrication.
Therefore, it would be most useful to be able to monitor stress during semiconductor device fabrication with the aim of modifying processes so as to reduce, or at least control, the stress and its resultant effects.
SUMMARY OF THE INVENTION
The invention disclosed herein presents a method and related structures that enable monitoring of stress acting upon a semiconductor structure. A method and apparatus for measuring the stress at microscopic levels is disclosed. The invention relies on the dimensional dependence between the width of a device and the inherent resistivity in the device.
The present invention discloses a method and apparatus used to measure the stress at a sub-chip (i.e., device and chip) level with resolution of stress effects on electrical conduction. The present invention permits obtaining data on the position dependence of stress effects on devices, including orientational effects on a semiconductor wafer or substrate used in production of VLSI devices and circuits. The present invention also allows monitoring of the dependence of stress on device size, particularly via wide-to-narrow diode behavior.
The present invention provides a structure for measuring stress in a semiconductor device comprising: a pn diode formed on the surface of a semiconductor device, said diode being bounded by a first shallow trench isolation region having predetermined dimensions; a diffusion region formed on the surface of the wafer, said diffusion region being bound by a second shallow trench isolation region having the same dimensions as the first shallow trench region; and contacts formed on said diode and diffusion region for passing current through the diode and through said diffusion region.
The present invention additionally provides a method of monitoring stress in a silicon substrate comprising the steps of: forming a first device comprising a pn diode in a first n-well region of a p-well formed in said silicon substrate, said pn diode having a geometry defined by a dielectric-filled trench; forming a second device comprising a p-type diffusion region in a second n-well region formed in said p-well region of said silicon substrate, said second n-well region having a geometry substantially the same as the geometry of said first n-well region and defined by a dielectric-filled trench; subtracting a first current measurement through said second device from a first current measurement from said first device.
The present invention further provides a method of using a stress monitor structure formed in a semiconductor wafer comprising the steps of: applying a current to the stress monitor structure; measuring a resultant bias voltage induced in the stress monitor structure by the current; comparing the stress-induced resultant bias voltage to a reference non-stress-induced bias voltage; and determining the amount of stress-induced electrical parameter variations in the semiconductor wafer.
The present invention also provides a stress monitoring unit comprising: a semiconductor material forming a base structure, said base structure containing a diode structure and a non-diode structure; said diode structure formed in the semiconductor material; said non-diode structure including a plurality of isolation trenches surrounding the diode structure, said isolation trenches being filled with a dielectric material; a system for applying an electrical potential across the diode structure, thereby inducing a diode current to flow through the diode structure; a system for measuring the diode current; and a system for translating the amount of diode current measured into dimensional units representing the stress on the base structure.
The present invention also discloses a stress monitoring set comprising: at least one pair of diode devices, or an array or plurality of diode devices, said pair consisting of a first device and a second device, wherein said first device is a reference device, and said second device (or array of secondary devices) is (are) a measurement device.
The present invention additionally discloses a stress monitoring system for monitoring mechanical stress in a semiconductor substrate containing trench isolation regions comprising: a semiconductor material forming a base structure, said base structure containing a diode structure and a non-diode structure; said diode structure formed in the semiconductor material; said non-diode structure including a plurality of isolation trenches surrounding the diode structure, said isolation trenches being filled with a dielectric material; a system for applying an electrical potential across the diode structure, thereby inducing a diode current to flow through the diode structure; a system for measuring the diode current; and a system for translating the amount of diode current measured into dimensional units representing the stress on the base structure.
REFERENCES:
patent: 4125820 (1978-11-01), Marshall
patent: 4144493 (1979-03-01), Lee et al.
patent: 6265729 (2001-07-01), Nelson et al.
patent: 6291834 (2001-09-01), Hasegawa
patent: 6339229 (2002-01-01), Shiga et al.
patent: 406349919 (1994-12-01), None
IBM Technical Disclosure Bulletin, vol. 34, No. 12, May 1992, On-Chip Electromigration Sensor Using Silicon Device, pp. 197-198.
Adams Edward D.
Ballantine Arne W.
Kontra Richard S.
Loiseau Alain
Slinkman James A.
Chaudhuri Olik
International Business Machines - Corporation
Pham Hoai
Schmeiser Olsen & Watts
Walter, Jr. Howard J.
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