Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-16
2004-07-20
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S723000, C438S756000
Reexamination Certificate
active
06764898
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the formation of a gate stack by an integrated plasma etch of gate and gate dielectric layers. The invention further relates to integration of high-K dielectric materials into existing semiconductor fabrication processes.
BACKGROUND ART
Fabrication of a semiconductor device and an integrated circuit thereof begins with a semiconductor wafer and employs various processes, such as film formation, ion implantation, photolithography, etching and deposition techniques to form various structural features in or on a semiconductor wafer to attain individual circuit components which are then interconnected to ultimately form an integrated semiconductor circuit. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
There is a demand for very large-scale and ultra large-scale integration devices employing high performance metal-oxide-semiconductor (MOS) devices. MOS devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region separating the source/drain regions. Above the channel region is typically a thin gate dielectric material, usually referred to as a gate oxide, and a conductive gate comprising conductive polysilicon or another conductive material such as polysilicon-germanium, a silicide or a metal. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, and complementary MOS (CMOS) devices employing both p-channel and n-channel devices are formed on a common substrate. MOS technology offers advantages of significantly reduced power density and dissipation as well as increased reliability, circuit performance and cost advantages.
The drive towards increased miniaturization and the resultant limits of conventional gate oxide layers have served as an impetus for the development of newer, high dielectric constant (“high-K”) materials as substitutes for conventional silicon dioxide-based gate oxide layers. Since the drain current in a MOS device is inversely proportional to the gate oxide thickness, the gate oxide is typically made as thin as possible commensurate with the material's breakdown potential and reliability.
Decreasing the thickness of the gate oxide layer between the gate electrode and the source/drain extension regions together with the relatively high electric field across the gate oxide layer, can undesirably cause charge carriers to tunnel across the gate oxide layer. This renders the transistor “leaky”, degrading its performance. To alleviate this problem, high-K dielectric materials are used as the gate dielectric. Herein, a high-K gate oxide may be referred to as a high-K gate dielectric material layer, in order to emphasize that the gate dielectric comprises a high-K dielectric material rather than silicon dioxide, which is often referred to simply as “oxide”.
When integrating new materials and or processes into the fabrication of a semiconductor device, there is a strong need to do so with as little change as possible to existing facilities and equipment and to reduce the number of additional steps required by the new materials and processes. In addition, it is desirable to reduce the number of times a semiconductor wafer is handled or transferred during fabrication. As a result of new materials and/or processes, it is often necessary to address new problems presented by the new materials and/or processes which are to be integrated into existing processes, and it is sometimes possible to combine steps which would otherwise be discrete.
One problem with the addition of high-K dielectric materials to semiconductor devices arises during fabrication. In conventional devices, in which silicon dioxide is applied as a layer on a semiconductor wafer and a portion of the layer forms a gate dielectric, in most processes the portions of the layer not forming the gate dielectric can be allowed to remain on the other surfaces of the wafer. Unlike such silicon dioxide layers, when a layer of high-K dielectric material is applied as a layer and a portion of this layer is to be used as the gate dielectric, the remaining portions of the high-K dielectric material layer may be not wanted or even may be deleterious, and so should be removed from the wafer. The process steps useful for removal of such high-K dielectric material have not been fully defined. In particular, since the chemistry of the high-K dielectric materials differs from that of silicon dioxide and other “standard-K” dielectric materials, the chemistry used to remove these latter materials may not be optimal for removal of high-K dielectric materials.
Thus, a problem exists in integrating high-K dielectric materials into a fabricating process, specifically the problem of removing high-K dielectric material from selected areas of a semiconductor wafer. As a result, a process is needed for removing high-K dielectric materials from selected areas of a semiconductor wafer, in which the high-K dielectric material may be removed as simply as possible, while introducing a minimum number of additional steps into the fabrication process.
DISCLOSURE OF INVENTION
In one embodiment, the present invention relates to a process of fabricating a semiconductor device, including steps of providing a semiconductor wafer; depositing on the semiconductor wafer at least one layer comprising a high-K dielectric material layer, and subsequently removing a selected portion of the at least one layer comprising a high-K dielectric material by implanting ions into the selected portion, and removing the selected portion by etching, in which the implanted ions increase an etch rate relative to an etch rate without the implanting.
In another embodiment, the present invention relates to a process of fabricating a semiconductor device, including steps of providing a semiconductor wafer; depositing on the semiconductor wafer at least one layer comprising a high-K dielectric material; depositing on the at least one layer comprising a high-K dielectric material a layer comprising polysilicon or polysilicon-germanium; removing portions of the layer comprising polysilicon or polysilicon-germanium; and removing a selected portion of the at least one layer comprising a high-K dielectric material by implanting ions into the selected portion, and removing the selected portion by etching, in which the implanted ions increase an etch rate relative to an etch rate without the implanting.
In another embodiment, the present invention relates to a process of fabricating a semiconductor device, including steps of providing a semiconductor wafer; depositing on the semiconductor wafer at least one layer comprising a high-K dielectric material layer; depositing on the at least one layer comprising a high-K dielectric material at least one gate layer; forming a gate electrode by removing portions of the at least one gate layer; and removing a selected portion of the at least one layer comprising a high-K dielectric material by implanting ions into the selected portion, and removing the selected portion by plasma etching, in which the implanted ions increase an etch rate of the selected portion relative to an etch rate without the implanting.
Thus, the present invention provides a method for etching a selected portion of a layer comprising a high-K dielectric material, thus simplifying and facilitating removal of the selected portion of the high-K dielectric material. The present invention provides a solution to the problem of removing high-K dielectric material from areas of a semiconductor wafer, by ena
En William G.
Jeon Joong S.
Lin Ming-Ren
Ngo Minh Van
Advanced Micro Devices , Inc.
Everhart Caridad
Renner , Otto, Boisselle & Sklar, LLP
LandOfFree
Implantation into high-K dielectric material after gate etch... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Implantation into high-K dielectric material after gate etch..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Implantation into high-K dielectric material after gate etch... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3198107