Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-10-02
2007-10-02
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S221000, C257SE21546
Reexamination Certificate
active
11320221
ABSTRACT:
A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI regions define a first active region in the first device region and a second active region in the second device region, forming an insulation mask over the STI region and the first active region in the first device region wherein the insulation mask does not extend over the second device region, and performing a stress-tuning treatment to the semiconductor substrate. The first active region and second active region have tensile stress and compressive stress respectively. An NMOS and a PMOS device are formed on the first and second active regions, respectively.
REFERENCES:
patent: 6037018 (2000-03-01), Jang et al.
patent: 6605502 (2003-08-01), Iyer et al.
patent: 2005/0064646 (2005-03-01), Chidambarrao et al.
patent: 2005/0179112 (2005-08-01), Belyansky et al.
patent: 2005/0285150 (2005-12-01), Birner et al.
patent: 2006/0019444 (2006-01-01), Lu et al.
patent: 2006/0228851 (2006-10-01), Sadaka et al.
Ortolland, C., et al., “Electrical Characterization and Mechanical Modeling of Process Induced Strain in 65 nm CMOS Technology,” IEEE, 2004, pp. 137-140.
Ishibashi, M., et al., “Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond,” Japanese Journal of Applied Physics, vol. 44, No. 48, 2005, pp. 2152-2156.
Sheu, Y. M., et al., “Impact of STI Mechanical Stress in Highly Scaled MOSFETs,” IEEE, 2003, pp. 269-272.
Huang Yu-Lien
Lien Hao-Ming
Tao Hun-Jan
Tseng Kai-Ting
Yeh Ling-Yen
Geyer Scott B.
Patel Reema
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Hybrid STI stressor with selective re-oxidation anneal does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hybrid STI stressor with selective re-oxidation anneal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hybrid STI stressor with selective re-oxidation anneal will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3841622