Highly reliable amorphous high-k gate dielectric ZrOXNY

Details Highly reliable amorphous high-k gate dielectric ZrOXNY Highly reliable amorphous high-k gate dielectric ZrOXNY

2002-01-17

2004-07-27

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S587000, C438S785000

Reexamination Certificate

active

06767795

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to semiconductor devices and device fabrication. Specifically, the invention relates to gate dielectric layers of transistor devices and their method of fabrication.
BACKGROUND OF THE INVENTION
In the semiconductor device industry, particularly in the fabrication of transistors, there is continuous pressure to reduce the size of devices such as transistors. The ultimate goal is to fabricate increasingly smaller and more reliable integrated circuits (ICs) for use in products such as processor chips, mobile telephones, or memory devices such as DRAMs. The smaller devices are frequently powered by batteries, where there is also pressure to reduce the size of the batteries, and to extend the time between battery charges. This forces the industry to not only design smaller transistors, but to design them to operate reliably with lower power supplies.
A common configuration of a transistor is shown in FIG.
1
. While the following discussion uses
FIG. 1
to illustrate a transistor from the prior art, one skilled in the art will recognize that the present invention could be incorporated into the transistor shown in
FIG. 1
to form a novel transistor according to the invention. The transistor
100
is fabricated in a substrate
110
that is typically silicon, but could be fabricated from other semiconductor materials as well. The transistor
100
has a first source/drain region
120
and a second source/drain region
130
. A body region
132
is located between the first source/drain region and the second source/drain region, the body region
132
defining a channel of the transistor with a channel length
134
. A gate dielectric, or gate oxide
140
is located on the body region
132
with a gate
150
located over the gate dielectric. Although the gate dielectric can be formed from materials other than oxides, the gate dielectric is typically an oxide, and is commonly referred to as a gate oxide. The gate may be fabricated from polycrystalline silicon (polysilicon) or other conducting materials such as metal may be used.
In fabricating transistors to be smaller in size and reliably operating on lower power supplies, one important design criteria is the gate dielectric
140
. A gate dielectric
140
, when operating in a transistor, has both a physical gate dielectric thickness and an equivalent oxide thickness (EOT). The equivalent oxide thickness quantifies the electrical properties, such as capacitance, of a gate dielectric
140
in terms of a representative physical thickness. EOT is defined as the thickness of a theoretical SiO
2
layer that describes the actual electrical operating characteristics of the gate dielectric
140
in the transistor
100
. For example, in traditional SiO
2
gate oxides, a physical dielectric thickness may be 5.0 nm, but due to undesirable electrical effects such as gate depletion, the EOT may be 6.0 nm. A gate dielectric other than SiO
2
may also be described electrically in terms of an EOT. In this case, the theoretical dielectric referred to in the EOT number is an equivalent SiO
2
oxide layer. For example, SiO
2
has a dielectric constant of approximately 4. An alternate dielectric with a dielectric constant of 20 and a physical thickness of 100 nm would have an EOT of approximately 20 nm=(100*(4/20)), which represents a theoretical SiO
2
gate oxide.
Lower transistor operating voltages and smaller transistors require thinner equivalent oxide thicknesses (EOTs). A problem with the increasing pressure of smaller transistors and lower operating voltages is that gate dielectrics fabricated from SiO
2
are at their limit with regards to physical thickness and EOT. Attempts to fabricate SiO
2
gate dielectrics thinner than today's physical thicknesses show that these gate dielectrics no longer have acceptable electrical properties. As a result, the EOT of a SiO
2
gate dielectric
140
can no longer be reduced by merely reducing the physical gate dielectric thickness.
Attempts to solve this problem have led to interest in gate dielectrics made from dielectric materials other than SiO
2
. Certain alternate dielectrics have a higher dielectric constant (k), which allows the physical thickness of a gate dielectric
140
to be the same as existing SiO
2
limits or thicker, but provides an EOT that is thinner than current SiO
2
limits.
A problem that arises in forming an alternate dielectric layer on the body region of a transistor is the process in which the alternate dielectric is formed on the body region. Recent studies show that the surface roughness of the body region has a large effect on the electrical properties of the gate dielectric, and the resulting operating characteristics of the transistor. The leakage current through a physical 1.0 nm gate dielectric increases by a factor of 10 for every 0.1 increase in the root-mean-square (RMS) roughness. In forming an alternate dielectric layer on the body region of a transistor, a thin layer of the alternate material to be oxidized (typically a metal) must first be deposited on the body region. Current processes for depositing a metal or other alternate layer on the body region of a transistor are unacceptable due to their effect on the surface roughness of the body region.
FIG. 2A
shows a surface
210
of a body region
200
of a transistor. The surface
210
in the Figure has a high degree of smoothness, with a surface variation
220
.
FIG. 2B
shows the body region
200
during a conventional sputtering deposition process stage. During sputtering, particles
230
of the material to be deposited bombard the surface
210
at a high energy. When a particle
230
hits the surface
210
, some particles adhere as shown by particle
235
, and other particles cause damage as shown by pit
240
. High energy impacts can throw off body region particles
215
to create the pits
240
. A resulting layer
250
as deposited by sputtering is shown in FIG.
2
C. The deposited layer/body region interface
255
is shown following a rough contour created by the sputtering damage. The surface of the deposited layer
260
also shows a rough contour due to the rough interface
255
.
In a typical process of forming an alternate material gate dielectric, the deposited layer
250
is oxidized to convert the layer
250
to an oxide material. Existing oxidation processes do not, however, repair the surface damage created by existing deposition methods such as sputtering. As described above, surface roughness has a large influence on the electrical properties of the gate dielectric and the resulting transistor.
What is needed is an alternate material gate dielectric that is more reliable at existing EOTs than current gate dielectrics. What is also needed is an alternate material gate dielectric with an EOT thinner than conventional SiO
2
. What is also needed is an alternative material gate dielectric with a smooth interface between the gate dielectric and the body region. Because existing methods of deposition are not capable of providing a smooth interface with an alternate material gate dielectric, what is further needed is a method of forming an alternate material gate dielectric that maintains a smooth interface.
Additionally, at higher process temperatures, any of several materials used to fabricate the transistor, such as silicon, can react with other materials such as metals or oxygen to form unwanted silicides or oxides. At high process temperatures, materials such as dopants can also migrate to unwanted areas, changing the desired structure or composition profile. What is needed is a lower temperature process of forming gate dielectrics that prevents migration and the formation of unwanted byproduct materials.
SUMMARY OF THE INVENTION
A method of forming a gate dielectric on a surface such as a transistor body region is shown where a metal layer is deposited by thermal evaporation on the body region. The metal layer is then oxidized to convert the metal layer to a metal oxide layer. The metal layer is also nitrided to form a metal oxynitride layer. In one

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