Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-24
2001-11-27
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000
Reexamination Certificate
active
06323074
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the protection of integrated circuits from electrostatic discharge (ESD), and more particularly to the protection of high voltage NMOS transistors by a parasitic silicon controlled rectifier (SCR) which triggers at a very low voltage.
2. Description of the Related Art
The protection of integrated circuits from electrostatic discharge (ESD) is a subject which has received a lot of attention from circuit designers because of the serious damage that ESD can wreak as device dimensions are reduced. Workers in the field and inventors have proposed many solutions, many trying to solve the problem of protecting sub-micron devices while still allowing them to function unencumbered and without undue, or zero, increase of silicon real estate. The main thrust of ESD protection for MOS devices is focused on the use of parasitic npn and pnp bipolar transistors, which together form a silicon controlled rectifier (SCR). Unwanted as this SCR normally is, it can safely discharge dangerous ESD voltages as long as its trigger voltage is low enough to protect those MOS devices of which it is a part.
FIG. 1
is a schematic cross-section of a high voltage n-channel metal oxide semiconductor (NMOS) device structure of the prior art showing a p-substrate
11
, an n-type doped drain (ndd) area
12
with an n+ drain
13
, and an n+ source
14
with a lightly doped drain (ldd) implant
15
. A polysilicon gate
17
with sidewall spacers
18
on either side covers the space between the drain
13
and the source
14
.
FIG. 2
is a cross section of an implementation of the same structure as shown in
FIG. 1
, showing four n-channel transistors T
1
to T
4
in a p-substrate
11
. Transistor T
1
is comprised of n+ source
14
, gate
17
, ndd area
12
with an n+ drain
13
diffused into it. Transistor T
2
is comprised of the same ndd area
12
with n+ drain
13
, gate
218
, and n+ source
220
, which is connected to ground. A p+ region
222
is implanted adjacent to n+ source
14
and both are connected to ground
229
. As is evident from
FIG. 2
, transistors T
3
and T
4
are mirror images of transistors T
1
and T
2
. This arrangement can be repeated as many times as necessary and depends on the current capacity desired. Note parasitic bipolar npn transistors Q
1
and Q
2
, their emitters, bases, and collectors formed by n+ sources
14
and
220
, p-substrate
11
and ndd area
12
, respectively. Their bases are connected to p+ region
222
via parasitic resistors R
1
, where these resistors symbolize the intrinsic resistance of p-substrate
11
. Transistors T
3
and T
4
along with parasitic npn bipolar transistors Q
3
and Q
4
form a mirror image to the arrangement comprised of transistors T
1
, T
2
, Q
1
, and Q
2
.
FIG. 3
is the equivalent-circuit diagram of FIG.
2
. It is apparent that the n-channel transistors T
1
to T
4
and parasitic npn transistor Q
1
to Q
4
are paralleled and that their bases are tied to ground via resistors R
1
. This explains why the electrostatic discharge (ESD) failure threshold voltage of the high voltage NMOS devices is very low, because its snapback voltage is very high, sometimes as high as 10 Volt or more. Despite the high and unstable snapback voltage power damage still occurs.
Other related art is described in the following U.S. Patents which propose low voltage lateral SCRs (LVTSCR), modified lateral SCRs (MLSCR), PMOS-trigger lateral SCRs (PTLSCR), NMOS-trigger lateral SCRs (NTLSCR), and modified PTLSCRs and NTLSCRs to control electrostatic discharge:
U.S. Pat. No. 5,959,820 (Ker et al.) proposes two or more cascoded low voltage triggering SCRs (LVTSCR) which are cascoded in series by coupling control gates in common and with an anode and a cathode of an LVTSCR coupled between the power supplies. Other devices utilized are and NMOS-controlled lateral SCRs (NCLSCR) and PMOS-controlled lateral SCRs (PCLSCR)
U.S. Pat. No. 5,894,153 (Walker et al.) describes an integrated circuit with a pad which is protected by an SCR which conducts ESD pulses from the pad to a current sink. The SCR includes a subregion underneath a field oxide that has a field implant that increases the dopant concentration. The field implant lowers the SCR trigger voltage, so that the SCR triggers before an ESD pulse can cause latchup damage.
U.S. Pat. No. 5,541,801 (Lee et al.) uses three LVTSCRs which are connected between V
dd
, the circuit to be protected, and V
ss
. Each of the SCRs uses a PMOS/NMOS transistor to lower the trigger voltage. The gates of the PMOS/NMOS transistors are each in turn connected via linked terminals of trigger gates to the circuit to be protected.
U.S. Pat. No. 5,455,436 (Cheng) teaches the use of a non-LDD NMOS junction which forms the equivalent npn transistor of the protective SCR structure. The abrupt drain junction produces a lower avalanche breakdown voltage than the LDD junction and triggers the SCR during an ESD pulse.
It should be noted that none of the above-cited examples of the related art utilize a p+ diffusion and an n-well to the high voltage NMOS drain side to provide a snap-back voltage of less than 2 Volt, a high Human Body Model (HBM) ESD Passing Voltage of up to 8 kVolt, as is proposed subsequently.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an ESD device for protecting NMOS transistors, where the SCR of that ESD device has a snapback voltage of less than 2 Volt and where the NMOS transistors and the SCR are integrated.
Another object of the present invention is to reduce the size of the silicon real estate for the combination of NMOS and SCR.
A further object of the present invention is to provide a HBM ESD Passing Voltage of 8,000 Volt.
These objects have been achieved by providing two n-channel transistors which share an n-type doped drain (ndd) area. The ndd area has implanted two n+ drains (one for each of the two transistors) and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The p+ diffusion and the n-well together form the emitter and base of a parasitic pnp bipolar transistor, respectively. The p-substrate of the semiconductor wafer forms the collector of the pnp transistor. The n-well also forms the collector of two parasitic npn bipolar transistors, while the p-substrate forms the bases. The n+ sources of the two n-channel transistors form the emitters. The pnp transistor and the two npn transistors create the aforementioned (parasitic) SCR. The low triggering voltage of the SCR is achieved by having the parasitic npn transistors of the SCR in parallel with one of the NMOS transistors by sharing the n-well (collector/drain), p-substrate (base/channel region), and an adjacent n+ diffusion (emitter/source) in the p-substrate, as already detailed above. The high HBM ESD Passing Voltage is made possible by having the n-well straddle the n+ drains of the NMOS transistors and by the combination of the ndd area and the n-well.
REFERENCES:
patent: 5455436 (1995-10-01), Cheng
patent: 5541801 (1996-07-01), Lee et al.
patent: 5869873 (1999-02-01), Yu
patent: 5894153 (1999-04-01), Walker et al.
patent: 5959820 (1999-09-01), Ker et al.
patent: 6066879 (2000-05-01), Lee et al.
Jiang Jyh-Min
Lee Jian-Hsing
Liu Kuo-Chio
Liu Ruey-Hsin
Ackerman Stephen B.
Le Dung A
Nelms David
Saile George O.
Taiwan Semiconductor Manufacturing Company
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