Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Sidewall base contact
Inventor
active
High voltage ESD protection device with very low snapback...
High voltage ESD protection device with very low snapback...
High voltage transistor using P+ buried layer
Method of fabricating a high voltage transistor using...
Method of forming a HVNMOS with an N+ buried layer...
No associations
LandOfFree
Jyh-Min Jiang does not yet have a rating. At this time, there are no reviews or comments for this inventor.
If you have personal experience with Jyh-Min Jiang, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Jyh-Min Jiang will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-P-2016200