High-density plasma etching of carbon-based low-k materials...

Details High-density plasma etching of carbon-based low-k materials... High-density plasma etching of carbon-based low-k materials...

1998-09-18

2001-09-04

Gulakowski, Randy (Department: 1746)

Etching a substrate: processes

Gas phase etching of substrate

Application of energy to the gaseous etchant or to the...

C216S067000, C216S072000, C438S710000, C438S725000

Reexamination Certificate

active

06284149

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to etching of materials. In particular, the invention relates to plasma etching of carbon-based materials included in integrated circuit chips.
BACKGROUND ART
The level of integration and speed in semiconductor integrated circuits continue to increase. The next generation of dynamic memories will have a capacity of 256 Mb and that of microprocessors will have upwards of ten million transistors. Further generations are being planned. Clock rates are exceeding 300 MHz and are expected to exceed 1 GHz. The increased level of integration has been accomplished in part by shrinking the lateral sizes of the individual components.
However, the increasing proximity of features, in particular the long conductive interconnects extending horizontally on a complex integrated circuit, has introduced the problem of unintended interactions between those features. A complex integrated circuit must include a large number of horizontal interconnects linking active circuits in one part of the integrated circuit to those in another part. Simultaneous with the decrease in feature sizes, the overall size of the integrated circuit has continued to somewhat increase. As a result, the length of the interconnects, which are often laid in parallel for a sizable distance of their runs, has increased or at the best not decreased, and their separation in the horizontal plane has significantly decreased. The amount of electrical coupling, more precisely expressed in terms of parasitic capacitance, between such lines is generally proportional to the ratio of their length to their separation. That is, the coupling necessarily increases with decreasing line separation unless the overall size of the chip is reduced, and it is unlikely that chip size will be reduced in the long term.
Although the coupling problem seems to be worse within respective wiring levels, inter-level coupling can occur across the thin inter-level dielectric layers interposed between multiple horizontal wiring levels. In advanced integrated circuits, particularly those of microprocessors and other complex logic, there may be five or more wiring levels to provide the complicated interconnection paths. The thickness of these inter-level dielectric layers appears to be limited at somewhat less 1 &mgr;m because of dielectric breakdown. However, even at these thicknesses, inter-level capacitance and resultant inter-signal coupling can become problems.
Another way of viewing this problem is to consider the RC charging time &tgr; between a long interconnect and a large grounded neighboring and parallel feature. The charging time may be represented by
&tgr;=R·C,  (1)
where R is the resistance of the conductive interconnect and C is the capacitance between the interconnect and the grounded feature. The equation is somewhat more complicated for inter-line interaction, but the effect is much the same. For the extremely high speed operation required of advanced integrated circuits, the speed may be limited by the time constant associated with interconnects, which can be characterized by a maximum operation frequency f
max
,
f
max
<
1
R
·
C
(
2
)
although there may be other factors near unity in this relationship. Generally in advanced circuits, the intra-level capacitance between parallel horizontal interconnects, such as in an internal bus extending over a substantial fraction of the chip, rather than the inter-level capacitance limits the operating speed of the chip.
Up till the present time, the increased speed has been accomplished in large part by decreasing the feature size and in particular decreasing the polygate length of the transistor, which increases its speed. However, as the feature sizes decrease below 0.18 &mgr;m, the effects of the metallization begin to dominate. Therefore, the composition of the metallization and the dielectric constant of the insulator begin to dominate.
One of the motivators for changing from aluminum to copper for advanced integrated circuits as the material of the interconnect is to reduce the value of R because of the lower resistivity of copper compared to aluminum, the conventional material as of now. It is greatly desired that this substitution of copper for aluminum as the metallization material not be compromised by a concurrent increase in the value of the inter-line capacitance C across the dielectric material as the feature sizes of integrated circuits further decrease.
The electrical characteristics of a dielectric material are quantified by its resistivity and its dielectric constant. For an insulator in an integrated circuit, the resistivity must be fairly high, approximately 10
14
ohm-cm or higher. The capacitance C of an planar capacitive structure, whether intentional or parasitic, can be represented as
C
=
k
·
A
d
,
(
3
)
where A is the area of the capacitive plates, d is the gap between the plates, and k is the dielectric constant of the material filling the gap. The relationship is somewhat more complex for interconnects, but the important factors are the same. For an interconnect of constant width, its area A increases with its length L. Reduced dielectric constant k results in reduced capacitance, thus reducing the cross-talk and coupling, thus allowing increased operating speeds.
At the present time, the most common form of inter-level dielectric for integrated circuits is silicon dioxide or related silicate glasses, such as BPSG. These are all silicon-based materials having the approximate chemical composition SiO
2
. Hereafter, these will be collectively referred to as silica. The dielectric constant k for silica is between 3.9 and 4.2. That for Si
3
N
4
, another common insulating material in present day integrated circuits, is even higher—7.5. For these reasons, there has been much recent interest in low-k dielectrics having a dielectric constant lower than 3.9.
Several low-k materials have been proposed for use as inter-level dielectric. For use in integrated circuit fabrication, any such material should at a minimum be compatible with other conventional chip processing steps. Some proposed low-k materials are silicon-based, for example, fluorinated silica glass (FSG, k=3.5), hydrophobic porous spin on glass (HPS, k=2.5~3), hydrogen-silsesquioxane (HSQ, k=2.5~2.9). Others are carbon-based, as will be discussed later. By a carbon-based material is meant a material containing on an atomic basis more carbon than either or both of silicon or oxygen. In contrast, a silicon-based material contains more silicon than carbon and is typically based on SiO
2
or Si
3
N
4
.
An example of an advanced structure to which it is desired to apply low-k dielectrics is a dual-damascene via, illustrated isometrically in
FIG. 1. A
via is an electrical contact through an inter-level dielectric layer separating two levels of metallization. A substrate
10
includes a copper horizontal interconnect
12
formed in its surface. Over the substrate are formed a lower stop layer
14
, a lower dielectric layer
16
, an upper stop layer
18
, and an upper dielectric layer
20
. The stop layers
14
,
18
are dielectric layers having etching characteristics different than those of the dielectric layers
16
,
20
such that a selective etch can be used which etches the dielectric layer but stops on the stop layer. One or more via holes
22
extend. through the lower dielectric layer
16
and the two stop layers
14
,
18
down to corresponding copper interconnects
12
, only one being shown in FIG.
1
. The portion of the lower stop layer
14
at the bottom of the via hole
22
is removed in a post-etch soft plasma treatment following the main etching steps. A trench
24
extends through the upper dielectric layer
20
and connects at its bottom with the via holes
22
.
There are two principal techniques for forming the dual-damascene structure, the self-aligned process and the counterbore dual-damascene process. In the self-aligned dual-damascene process, the lower stop layer
14
, the lower dielect

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