Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-07-11
1999-02-02
Chaudhuri, Olik
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438275, 257401, H01L 218238
Patent
active
058664459
ABSTRACT:
A method for making a CMOS device includes: forming a PMOS region 60 of a first conductivity type; forming an NMOS region 62 of a second conductivity type adjacent the PMOS region 60; forming an insulating layer 64 and 66 over the PMOS region 60 and the NMOS region 62 such that the insulating layer is thinner over the PMOS region than over the NMOS region; forming a common gate 48 over the insulating layer 64 and 66; forming PMOS source/drain regions 40 and 42 of the second conductivity type in the PMOS region 60 and aligned to the common gate 48; and forming NMOS source/drain regions 44 and 46 of the first conductivity type in the NMOS region 62 and aligned to the common gate 48.
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Brady III Wade James
Chaudhuri Olik
Coleman William David
Donaldson Richard L.
Stewart Alan K.
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