Fabrication of shallow trench isolation structures with...

Details Fabrication of shallow trench isolation structures with... Fabrication of shallow trench isolation structures with...

2002-11-12

2004-03-23

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C296S067000, C296S067000, C296S067000, C296S067000, C296S067000, C296S067000, C296S067000, C438S978000

Reexamination Certificate

active

06709924

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of integrated circuits, and more particularly, to a method of fabricating shallow trench isolation structures with rounded corners and self-aligned gate, with a minimized number of processing steps.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, an integrated circuit device such as a MOSFET (metal oxide semiconductor field effect transistor)
100
is fabricated within an active area
102
of a semiconductor substrate
104
. The MOSFET
100
includes a drain region
103
, a source region
105
, a gate dielectric
106
, and a gate structure
108
, and such a MOSFET
100
is known to one of ordinary skill in the art of integrated circuit fabrication.
The active area
102
is defined by shallow trench isolation structures
110
formed to surround and electrically isolate the active area
102
. The semiconductor substrate
104
is typically comprised of silicon, and the shallow trench isolation structures
110
are comprised of a dielectric material such as silicon dioxide (SiO
2
) or a low-k dielectric material, as known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to
FIG. 2
, for forming shallow trench isolation structures, a layer of pad oxide
112
comprised of silicon dioxide (SiO
2
) is deposited on the semiconductor substrate
104
, and a layer of silicon nitride (Si
X
N
Y
)
114
is deposited on the layer of pad oxide
112
. Processes for depositing the layer of pad oxide
112
and the layer of silicon nitride
114
are known to one of ordinary skill in the art of integrated circuit fabrication. Referring to
FIGS. 2 and 3
, the layer of silicon nitride
114
, the layer of pad oxide
112
, and the semiconductor substrate
104
are patterned to form shallow trench openings
116
surrounding an active area
118
of the semiconductor substrate
104
. Processes for patterning the layer of silicon nitride
114
, the layer of pad oxide
112
, and the semiconductor substrate
104
to form the shallow trench openings
116
are known to one of ordinary skill in the art of integrated circuit fabrication.
In a typical process for patterning the layer of silicon nitride
114
, the layer of pad oxide
112
, and the semiconductor substrate
104
to form the shallow trench openings
116
, bottom corners
120
and top corners
122
of the shallow trench openings
116
are formed to be relatively sharp, as known to one of ordinary skill in the art of integrated circuit fabrication. However, such sharp corners may result in the “kink effect” where uneven distribution of charge carriers leads to high electric fields at such corners, as known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to
FIGS. 3 and 4
, for rounding the bottom corners
120
of the shallow trench openings
116
, a thermal oxidation process is performed for forming liner oxide
130
at the walls of the shallow trench openings
116
. Such formation of the liner oxide
130
rounds the bottom corners
120
of the shallow trench openings
116
. However, nitrogen is an oxidation-retarding agent, as known to one of ordinary skill in the art of integrated circuit fabrication. Thus, in the prior art, the silicon nitride
114
disposed directly above the top corners
122
of the shallow trench openings
116
inhibit formation of the liner oxide
130
at the top corners
122
of the shallow trench openings
116
. Thus, the top corners
122
of the shallow trench openings
116
are not rounded after formation of the liner oxide
130
.
Referring to
FIGS. 4 and 5
, a trench dielectric material
132
such as silicon dioxide (SiO
2
) or a low-k dielectric material is deposited to fill the shallow trench openings
116
. Referring to
FIGS. 5 and 6
, materials on the semiconductor substrate
104
are polished down such that the trench dielectric material
132
is contained within the shallow trench openings
116
to form the shallow trench isolation structures
134
. Referring to
FIGS. 6 and 7
, the remaining silicon nitride
114
is etched away. Such processes for forming the shallow trench isolation structures
134
of
FIG. 7
are known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to
FIGS. 7 and 8
, an additional etch process such as a HF (hydrofluoric) dip is performed to etch away the pad oxide
112
and to etch away side portions of the shallow trench isolation structures
134
for exposing the top corners
122
near the shallow trench isolation structures
134
. Such an etch process is known to one of ordinary skill in the art of integrated circuit fabrication. Referring to
FIGS. 8 and 9
, an additional thermal oxidation process is performed to form additional top oxide
136
at the top corners
122
of the shallow trench isolation structures
134
for rounding such top corners
122
. However, such processing steps for exposing and rounding the top corners
122
near the shallow trench isolation structures
134
disadvantageously increase the number of processing steps in the prior art.
Referring to
FIGS. 10 and 11
, for fabricating a flash memory cell within the active area
118
of the semiconductor substrate
104
, a tunneling gate dielectric
140
is formed on the active area
118
of the semiconductor substrate
104
, and a floating gate
142
is formed on the tunneling gate dielectric
140
. In addition, a control gate dielectric
144
is formed on the floating gate
142
across the floating gates of a row of flash memory cells separated by shallow trench isolation structures
134
. Furthermore, a control gate material
146
is formed on the control gate dielectric
144
across such a row of flash memory cells. Such structures
140
,
142
,
144
, and
146
for a flash memory cell are known to one of ordinary skill in the art of electronics.
In the prior art of
FIG. 10
, the top surface of the control gate material
146
is substantially non-planar. Such a non-planar surface causes optical inference in subsequent photolithography processes such that a lower number of contacts may be formed. A lower number of contacts disadvantageously increases the number of interconnect levels. In addition, with such non-planar topology of the flash memory cell of
FIG. 10
, a lower number of rows of control gates may be formed for a disadvantageously lower density of flash memory cells that may be formed with such non-planar gate stack structures of FIG.
10
.
Furthermore, referring to
FIGS. 10 and 11
, with the prior art structures
140
,
142
,
144
, and
146
of the flash memory cells, if the structures
140
,
142
,
144
, and
146
are fabricated to be mis-aligned with the shallow trench isolation structures
134
, then the flash memory cell may be in-operative. For example in
FIG. 11
, the floating gate
134
and the control gate dielectric
144
are formed shifted too much to the right such that the control gate dielectric
144
makes contact with the tunneling gate dielectric
140
at area
150
. In that case, the flash memory cell comprised of such shifted floating gate
134
and control gate dielectric
144
is in-operative.
For proper operation of a flash memory cell, all four layers of the tunneling gate dielectric
140
, the floating gate
142
, the control gate dielectric
144
, and the control gate material
146
should be disposed over the active area
118
of the semiconductor substrate
102
. Thus, the groove
148
of the control gate dielectric
144
needs to be placed within the width of the shallow trench isolation structures
134
for the flash memory cell to be operative. The groove
148
of the control gate dielectric
144
separates two adjacent rows of floating gates, and thus, the groove
148
of the control gate dielectric
144
should be placed within the shallow trench isolation structures
134
.
However, with mis-alignment in stepper tools for forming the control gate dielectric
144
and especially with decreasing dimensions of integrated circuit devices, such alignment is difficult to achieve, especially as mis-alignment

Affiliated with

Also associated with

Rating

Fabrication of shallow trench isolation structures with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication of shallow trench isolation structures with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of shallow trench isolation structures with... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3189311