4. Semiconductor device manufacturing: process
  5. Coating with electrically or thermally conductive material
  6. To form ohmic contact to semiconductive material

Jeffrey A. Shields

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Borderless vias with HSQ gap filled patterned metal layers

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent

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Borderless vias with HSQ gap filled patterned metal layers

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent

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Borderless vias without degradation of HSQ gap fill layers

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate

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Borderless vias without degradation of HSQ gap fill layers

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent

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Buried silicide local interconnect with sidewall spacers and...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate

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Profile ID: LFUS-PAI-P-359966

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