Fabrication of a CMOS structure with a high-k dielectric...

Details Fabrication of a CMOS structure with a high-k dielectric... Fabrication of a CMOS structure with a high-k dielectric...

2011-01-04

2011-01-04

Fahmy, Wael M (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S591000, C438S592000, C438S658000, C438S660000, C257S369000, C257S392000, C257SE21438, C257SE21470

Reexamination Certificate

active

07863126

ABSTRACT:
A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.

REFERENCES:
patent: 6506676 (2003-01-01), Park
patent: 6790731 (2004-09-01), Zheng
patent: 6794232 (2004-09-01), Zheng
patent: 6879009 (2005-04-01), Zheng
patent: 7208353 (2007-04-01), Yagishita
patent: 7242064 (2007-07-01), Yagishita
patent: 7432567 (2008-10-01), Doris et al.
patent: 7528024 (2009-05-01), Colombo et al.
patent: 7655550 (2010-02-01), Schaeffer et al.
patent: 2002/0130340 (2002-09-01), Ma et al.
patent: 2004/0238859 (2004-12-01), Polishchuk et al.
patent: 2004/0245578 (2004-12-01), Park et al.
patent: 2005/0282329 (2005-12-01), Li
patent: 2006/0038236 (2006-02-01), Yamamoto
patent: 2009/0212369 (2009-08-01), Park et al.
patent: 2009/0218632 (2009-09-01), Cheng
patent: 2009/0263950 (2009-10-01), Koyama et al.
U.S. Appl. No. 11/745,994, filed May 8, 2007, B. B. Doris.
U.S. Appl. No. 12/037,158, filed Feb. 26, 2008, D. G. Park.
V. Narayanan et al., “IEEE VLSI Symposium”, p. 224, (2006).
Guha et al., Appl. Phys. Lett. 90, 092902 (2007).

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