Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-06-07
1998-01-27
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438253, 438199, H01L 218242
Patent
active
057122016
ABSTRACT:
A semiconductor fabrication process has been developed in which both DRAM and logic device structures are integrated on a single silicon chip. The process features combining process steps for both device types, while using only a single level of polysilicon for both a high capacity DRAM cell, as well as for a CMOS logic cell. The high capacity DRAM cell is composed of an overlying polysilicon storage gate structure, a thin dielectric layer, and an underlying doped semiconductor regions.
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Lee Jin-Yuan
Liang Mong-Song
Yoo Chue-San
Ackerman Stephen B.
Bowers Jr. Charles L.
Gurley Lynne A.
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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