Elevated source drain disposable spacer CMOS

Details Elevated source drain disposable spacer CMOS Elevated source drain disposable spacer CMOS

2002-06-14

2004-08-17

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S305000, C438S586000, C438S595000, C438S664000

Reexamination Certificate

active

06777298

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of making CMOS devices, and more particularly, to one with an elevated source and drain and optionally having a halo region.
2. Description of the Related Art Including Information Diclosed Under 37 CFR 1.97 and 1.98
As CMOS technology becomes smaller, e.g., less than 50 nm gate length, it becomes more and more difficult to improve the short channel device performance and at the same time maintain acceptable values for off-state leakage current.
One technique for trying to achieve this is the halo technique wherein extra dopant implant regions are next to the sources and drain extension regions. For this to work the junctions must be abrupt, see “CMOS Devices below 0.1 nm: How High Will Performance Go?”, by Y. Taur, et al., pp. 1-4. In particular, for sub 50 nm devices, not only the extension regions near the channel must be abrupt, i.e., less than 4 nm/decade, but the halo profile in proximity to the extension junction must be abrupt, i.e., less than 20 nm/decade.
Most of the prior art for the halo formation used a general approach wherein halo dopants are implanted at an angle ranging from 0° to 70° into the channel region. This prior art varied either the dose, halo dopants, or angle of halo implants for improving the device performance. The article “Halo Doping Effects in Submicron DI-LDD Device Design” by Christopher Codella et al., pp. 230-233, describes the optimum halo doses for improving the threshold voltage and the punch-through device characteristics. Punch-through stoppers was also discussed in the U.S. Pat. No. 5,320,974 by Atsushi Hori et al. which is similar to the conventional halo arrangements. The article “A 0.1 nm IHLATI (Indium Halo by Large Angle Tilt Implant) MOSFET for 1.0V Low Power Application” by Young Jin Choi et al. described the use of an indium halo and a large angle tilt for indium halo implants for improving the short channel characteristics. Other articles are “High Carrier Velocity and Reliability of Quarter-Micron SPI (Self-Aligned Pocket Implantation) MOSEFETs” by A. Hori et al. and “A 0.1-&mgr;m CMOS Technology with Tilt-Implanted Punchthrough Stopper (TIPS)” by T. Hori.
None of the prior art focussed attention on improving the abruptness of the halo dopant profiles in the area next to the channel. In these prior art situations, the halo dopants would have suffered enhanced transient diffusion and/or deactivation during contact and extension junction formation, and high thermal budget deep source/dran rapid thermal anneal (RTA) (typically 1000° C. for 5 seconds). Consequently, these much degraded halos severely compromised their usefulness for improving the short channel device characteristics, and this is especially the case for device channel width below 50 nm. Thus all the prior art approaches provide no means to minimize transient enhanced diffusion and/or deactivation of the halo dopants and hence cannot be used to create the abrupt super-halo (<20 nm/decade) in the region next to the channel area.
It is therefore desirable to have a process for making abrupt shallow PN juntions and haloes which does not cause dopant diffusion or deactivation.
BRIEF SUMMARY OF THE INVENTION
A method comprises forming source and drain regions; and thereafter forming source and drain extension regions.
A method comprises forming elevated and deep source and drain regions; forming source and drain extension regions; and thereafter forming source and drain contact regions at a temperature up to about 600° C. and an annealing time up to about one minute.


REFERENCES:
patent: 5320974 (1994-06-01), Hori et al.
patent: 5744395 (1998-04-01), Shue et al.
patent: 5770507 (1998-06-01), Chen et al.
patent: 5780350 (1998-07-01), Kapoor
patent: 6121100 (2000-09-01), Andideh et al.
patent: 6492670 (2002-12-01), Yu
patent: 6583016 (2003-06-01), Wei et al.
A 0.1-um CMOS Technology with Tilt-Implanted Punchthrough Stopper (TIPS).
High Carrier Velocity and Reliability of Quarter-Micron SPI (Self-aligned Pocket Implantation) MOSFETs.
1997 55thAnnual Device Research Conference Digest.
Halo Doping Effects in Submicron Di-LDD Device Decision.
CMOS Devices below 0.1 um: How High Will Performance Go?.

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