Electronic circuit comprising a test mode secured by...

Details Electronic circuit comprising a test mode secured by... Electronic circuit comprising a test mode secured by...

2011-04-19

2011-04-19

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S703000

Reexamination Certificate

active

07930605

ABSTRACT:
An electronic circuit includes configurable cells each having a test input and an output. The configurable cells are connected to one another in a chain in a predefined order via their test input and their output to form a test register based on receiving a chaining command signal. The electronic circuit also includes a detection circuit activated by the chaining command signal to produce a state signal representing a state of initialization of a first set of configurable cells A multiplexing circuit selectively connects the test input of each configurable cell to a second set of the configurable cells either to the output of a preceding configurable cell or to an output of a decoy data generator based on the state signal.

REFERENCES:
patent: 5574733 (1996-11-01), Kim
patent: 2003/0204801 (2003-10-01), Tkacik et al.
patent: 2008/0148118 (2008-06-01), Morgan et al.
patent: 1560033 (2005-08-01), None
Hely et al., Test Control for Secure Scan Designs, Test Symposium, European Tallinn, Estonia, May 22, 2005; pp. 190-195.

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