Electron mobility enhancement for MOS devices with nitrided...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21632

Reexamination Certificate

active

07544561

ABSTRACT:
A semiconductor structure includes a PMOS device and an NMOS device. The PMOS device includes a first gate dielectric on a semiconductor substrate, a first gate electrode on the first gate dielectric, and a first gate spacer along sidewalls of the first gate electrode and the first gate dielectric. The NMOS device includes a second gate dielectric on the semiconductor substrate, a second gate electrode on the second gate dielectric, a nitrided polysilicon re-oxidation layer having a vertical portion and a horizontal portion wherein the vertical portion is on sidewalls of the second gate electrode and the second gate dielectric and wherein the horizontal portion is on the semiconductor substrate, and a second gate spacer on sidewalls of the second gate electrode and the second gate dielectric, wherein the second gate spacer is on the horizontal portion of the nitrided polysilicon re-oxidation layer.

REFERENCES:
patent: 5648284 (1997-07-01), Kusunoki et al.
patent: 6780776 (2004-08-01), Qi et al.
patent: 7071067 (2006-07-01), Ahmad
patent: 2005/0164444 (2005-07-01), Burnham et al.
patent: 2006/0154425 (2006-07-01), Yang et al.
patent: 1501470 (2004-06-01), None
patent: 1815703 (2006-08-01), None
Authors: Paul G. Y. Tsui, Hsing-Huang Tseng, Marius Orlowski, Shih-Wei Sun, P. J. Tobin, Kimberly Reid, and William J. Taylor Title: Suppression of MOSFET Reverse Short Channel Effect N20 Gate Poly Reoxidation Process Publisher: IEDM Tech. Digest, pp. 501-504 (1994).
S. Kusunoki, M. Inuishi, T. Yamaguchi, K. Tsukamoto, and Y. Akasaka “Hot-carrier-resistant structure by re-oxidized nitrided oxide sidewall for highly reliable and high performance LDD MOSFETS” IEEE IEDM, Technical Digest, vol. 91, 1991, pp. 649-652.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electron mobility enhancement for MOS devices with nitrided... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electron mobility enhancement for MOS devices with nitrided..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electron mobility enhancement for MOS devices with nitrided... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4144608

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.