Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Utility Patent
1998-11-06
2001-01-02
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S782000, C438S788000
Utility Patent
active
06169039
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the fabrication of integrated circuits, and more particularly to forming low dielectric constant insulating layers between metal conductive lines that provide the interconnection between the active or passive elements of the integrated circuit. Further, the invention relates to the novel integrated circuit structures resulting therefrom.
BACKGROUND OF THE INVENTION
In very large scale integrated (VLSI) circuit devices, several wiring layers are required to connect together the active or passive elements in a VLSI semiconductor chip. The interconnection structure consists of thin conductive lines separated by insulation in one layer or level and connected through vias or studs from contacts of the elements of the semiconductor chip or to a similar layer in another level of interconnections. This interconnection structure is similar to a transmission line in that there is a propagation delay of the signals being transmitted in these wiring layers. The delay is referred to as RC delay because it generally relates to the resistance (R) of the material of the wire and the capacitance (C) between adjacent wires.
With the trend of higher and higher levels of integration in integrated circuits to ultra large scale integrated (ULSI) circuits, the space or gap between the conductive lines that is to be filled with insulation is becoming extremely narrow between some of the conductive lines, such as those that are about 0.5 microns and smaller. Such a narrow space or gap between conductive lines increases the capacitance and places greater demands on the insulating properties of the insulation between such conductive lines. Capacitance (C) is the product of dielectric constant of the insulting material times the area (A) of the opposing faces of the conductive line divided by the distance (D) between the conductive lines. With a decrease in distance (D), the capacitance (C) increases. Since signal delay of signals transmitted on the conductive line is controlled by the (RC) constant, an increase in capacitance (C) degrades the performance of the integrated circuit.
At present, thermal curing is the conventional approach for curing dielectric materials having a low dielectric constant (hereinafter referred to as low-k dielectric material). However, electron beams have also been used to cure low-k dielectric materials such as spin on glass (SOG), benzocyclobutine (BCB), and hydrogen silsesquioxanes (HSQ). Electron beam curing has advantages over conventional heat curing in that it produces low-k dielectric materials resistant to moisture and resistant to subsequent heating, and it adds mechanical strength.
However, a disadvantage of electron beam curing is that the dielectric constant of the low-k material is increased by the electron beam curing process. Because the dielectric constant of the low-k material is increased, correspondingly parasitic capacitance between conductive lines also increases. The increase in parasitic capacitance between conductive lines has a direct negative impact on VLSI and ULSI circuit performance.
Additionally, it is often necessary to etch vias through dielectric layers above conductive lines. Misalignment of the vias may cause etching through the dielectric material against the metal side wall of the conductive lines. This over etching causes a decrease in the insulating properties of the dielectric layer and an increase on the overall parasitic capacitance between the metal conductive lines.
Thus, there is a need and desire for a method of producing integrated circuits, including VLSI and ULSI circuit devices, that gain the advantages of electron beam curing of low-k dielectric materials while minimizing the negative impact of the increased dielectric constant. There is a need and desire for an integrated circuit having an insulating layer that will provide moisture resistance, thermal resistance, and mechanical support to metal conductive lines, but will only have a minor impact on the overall parasitic capacitance between metal conductive lines.
Further, there is a need and desire for a method of producing integrated circuit devices that minimize the yield loss due to metal-metal bridging between metal lines during subsequent processing that is caused by over etching against the side wall of metal lines in the process of etching vias or contacts, due to the misalignment of the vias or contacts.
Further still, there is a need and desire for an integrated circuit device having conductive lines separated by low-k dielectric materials that are resistant to moisture, resistant to subsequent heating steps, and mechanically strengthened, while maintaining a low parasitic capacitance between conductive lines.
SUMMARY OF THE INVENTION
The present invention relates to a method of making an insulating material on an integrated circuit. The integrated circuit has a silicon substrate, a dielectric stack formed on the silicon substrate, and at least one conductive metal line overlying the silicon substrate. The method includes depositing a first layer of low-k dielectric material to cover the at least one conductive metal line, exposing the first layer of low-k dielectric to an electron beam (E-beam), and depositing a second layer of low-k dielectric material to cover the first layer of low-k dielectric material.
The present invention further relates to an integrated circuit including a silicon substrate, a dielectric stack formed on the silicon substrate, at least one conductive metal line overlying the silicon substrate, a first layer of low-k dielectric material overlying the at least one conductive metal line, and a second layer of low-k dielectric material overlying the first layer of low-k dielectric material. The first layer of low-k dielectric material is electron beam (E-beam) cured.
The present invention still further relates to a method of forming an insulating material on a patterned surface of conductive lines separated by gaps and formed on a substrate. The method includes depositing a first layer of low-k dielectric material around the metal lines, curing the first layer of low-k dielectric material by exposing the low-k dielectric material to an electron beam, and depositing a second layer of low-k dielectric material over the first layer of low-k dielectric material.
The present invention still further relates to a method of forming an integrated circuit on a dielectric stack. The dielectric stack includes a silicon substrate underlying a first layer of low-k dielectric. The first layer of low-k dielectric underlies an electron-beam (E-beam) cured second layer of low-k dielectric. The method of forming the semiconductor includes forming conductive lines on the dielectric stack by selective etching, depositing a third layer of low-k dielectric material around the metal lines, curing the third layer of low-k dielectric material by exposing the third layer of low-k dielectric material to an electron beam, and depositing a fourth layer of low-k dielectric material over the third layer of low-k material.
REFERENCES:
patent: 5723908 (1998-03-01), Fuchida et al.
patent: 5972803 (1999-10-01), Shu et al.
patent: 5989983 (1999-11-01), Goo et al.
Zhao, B. Advanced Interconnect Systems for ULSI Technology, Proceedings on the 1998 5th International Conference on Solid-State and Integrated Circuit Technology. Oct. 21-23, 1998. pp. 43-46.
Hui, J.C.M. et al.. Integration of Low k Spin-on Polymer (SOP) Using Electron Beam Cure For Non-Etch-Back Application. 1998 Proceedings of the IEEE International Interconnect Technology Conference. Jun. 1-3, 1998. pp. 217-219.
Bang David
Lin Ming-Ren
Pramanick Shekhar
Advanced Micro Devices , Inc.
Chaudhuri Olik
Foley & Lardner
Peralta Ginette
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