Dual damascene interconnect structures having different...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S625000, C257SE21579, C257SE21585

Reexamination Certificate

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11174985

ABSTRACT:
Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

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patent: 5821168 (1998-10-01), Jain
patent: 5897369 (1999-04-01), Jun
patent: 6028362 (2000-02-01), Omura
patent: 6297149 (2001-10-01), Stamper
patent: 6383821 (2002-05-01), Young et al.
patent: 6984580 (2006-01-01), Dostalik et al.
patent: 2004/0108217 (2004-06-01), Dubin

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