DRAM processing methods

Details DRAM processing methods DRAM processing methods

2001-10-25

2003-06-17

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06579756

ABSTRACT:

TECHNICAL FIELD
This invention relates to capacitor processing methods, for example as found in logic and memory circuitry, and even more specifically to DRAM processing methods.
BACKGROUND OF THE INVENTION
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, If such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs and beyond will be on the order of 0.25 micron or less, and conventional dielectrics such as SiO
2
and Si
3
N
4
might not be suitable because of small dielectric constants.
Highly integrated memory devices, such as 256 Mbit DRAMs and beyond, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO
2
equivalent thickness.
Insulating inorganic metal oxide materials have high dielectric constants and low leakage current which make them attractive as cell dielectric materials for high density DRAMs and non-volatile memories. Such materials include tantalum pentoxide, barium strontium titanate, strontium titanate, barium titanate, lead zirconium titanate and strontium bismuth titanate. Using such materials enables the creation of much smaller and simpler capacitor structures for a given stored charge requirement, enabling the packing density dictated by future circuit design.
Despite the advantages of high dielectric constants and low leakage, insulating inorganic metal oxide materials suffer from many drawbacks. For example, all of these materials incorporate oxygen or are otherwise exposed to oxygen for densification to produce the desired capacitor dielectric layer. Densification or other exposure to an oxygen containing environment is utilized to fill oxygen vacancies which develop in the material during its formation. For example when depositing barium strontium titanate, the material as-deposited can have missing oxygen atoms that may deform its crystalline structure and yield poor dielectric properties. To overcome this drawback, for example, the material is typically subjected to a high temperature anneal in the presence of an oxygen ambient. The anneal drives any carbon present out of the layer and advantageously injects additional oxygen into the layer such that the layer uniformly approaches a stoichiometry of five oxygen atoms for every two tantalum atoms. The oxygen anneal is commonly conducted at a temperature of from about 400° C. to about 1000° C. utilizing one or more of O
3
, N
2
O and O
2
. The oxygen containing gas is typically flowed through a reactor at a rate of from about 0.5 slm to about 10 slm.
Unfortunately, such high temperature processing can degrade other substances in the circuitry. Such degradation can reduce the reliability of various circuit devices and has been viewed as a significant obstacle to incorporating high dielectric constant materials into integrated circuits.
SUMMARY
The invention comprises capacitor processing methods, for example as found in logic and memory circuitry, and even more specifically to DRAM processing methods. In but one implementation, a capacitor processing method includes forming a capacitor comprising first and second electrodes having a capacitor dielectric region therebetween. The first electrode interfaces with the capacitor dielectric region at a first interface. The second electrode interfaces with the capacitor dielectric region at a second interface. The capacitor dielectric region has a plurality of oxygen vacancies therein. After forming the capacitor, an electric field is applied to the capacitor dielectric region to cause oxygen vacancies to migrate towards one of the first and second interfaces. Oxygen atoms are preferably provided at the one interface effective to fill at least a portion of the oxygen vacancies in the capacitor dielectric region. Preferably at least a portion of the oxygen vacancies in the high k capacitor dielectric region are filled from oxide material comprising the first or second electrode most proximate the one interface.
In one implementation, a method of reducing oxygen vacancies in a high k capacitor dielectric region comprises causing oxygen vacancies to migrate towards an interface between the capacitor dielectric region and one of a pair of opposing capacitor electrodes under conditions effective to cause oxygen atoms present at the interface to fill at least a portion of the vacancies after fabrication of the capacitor electrodes and capacitor dielectric region.
In one implementation, a DRAM processing method includes forming DRAM circuitry comprising DRAM array capacitors having a common cell electrode, respective storage node electrodes, and a high k capacitor dielectric region therebetween. A voltage is applied to at least one of the first and second electrodes to produce a voltage differential therebetween under conditions effective to cause oxygen vacancies in the high k capacitor dielectric region to migrate toward one of the cell electrode or the respective storage node electrodes and react with oxygen to fill at least a portion of the oxygen vacancies in the capacitor dielectric region.
Other implementations are contemplated.


REFERENCES:
patent: 5889647 (1999-03-01), Hansen et al.
patent: 6281142 (2001-08-01), Basceri et al.
U.S. patent application Ser. No. 09/326,429, Basceri et al., filed Jun. 4, 1999.

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