Dishing and erosion monitor structure for damascene metal proces

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

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257621, 324671, 324688, 371 225, 437 8, 437974, H01L 2358, H01L 2940

Patent

active

057238740

ABSTRACT:
According to the preferred embodiment, an erosion and dishing monitor is provided that facilitates the accurate optimization of a planarization process as in semiconductor process. The dishing monitor comprises at least two monitor structure sets embedded in a semiconductor substrate, the monitor structure sets comprising a plurality of monitor structures connected together with a plurality of connective conductors. The erosion monitor comprises a plurality of elongated conductors embedded into a semiconductor substrate, the plurality of conductors having varying conductor widths and adjacent substrate widths.

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