Direct contact between high-κ/metal gate and wiring...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S201000, C438S231000, C438S239000, C438S285000, C438S299000, C257SE21438

Reexamination Certificate

active

07863123

ABSTRACT:
A low resistance contact is formed to a metal gate or a transistor including a High-κ gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.

REFERENCES:
patent: 6475906 (2002-11-01), Lee
patent: 7081393 (2006-07-01), Belyansky et al.
patent: 7405497 (2008-07-01), Jacobs et al.
patent: 7435652 (2008-10-01), Chen et al.
patent: 2004/0183204 (2004-09-01), Cave et al.
patent: 2005/0186792 (2005-08-01), Takahashi
patent: 2006/0192258 (2006-08-01), Tsuchiya et al.
patent: 2007/0257302 (2007-11-01), Kang et al.
patent: 2008/0164498 (2008-07-01), Taylor
patent: 2008/0311711 (2008-12-01), Hampp et al.
International Application No. PCT/EP2010/050295 Filing Date: Dec. 1, 2010 International Searching Authority—ISR and Written Opinion.

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