Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-01
2007-05-01
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S742000, C714S025000, C703S022000, C702S119000, C716S030000
Reexamination Certificate
active
10905734
ABSTRACT:
A digital logic test method for systematically testing a pipeline-structured integrated circuit chip is disclosed. The method includes the steps of: providing an integrated circuit chip capable of executing a plurality of instructions during a period of time, each of the instructions being executed according to a plurality of sequentially ordered operation segments, sorting the instructions, and designing a plurality of test patterns to test the integrated circuit according to the sorting result and STAGE test segments corresponding to the STAGE operation segments.
REFERENCES:
patent: 2002/0084273 (2002-07-01), Ming
Adir et al., “Piparazzi: A Test Program Generator for Micro-architecture Flow Verification”, Jun. 3, 2003, IEEE 10.1109/HLDVT 2003. 1252470, pp. 23-28.
Adir et al., “Genesys-Pro: Inovations in Test Program Generation for Functional Processor Verification”, Mar.-Apr. 2004, IEEE 10.1109/MDT.2004. 1277900, pp. 84-93.
Freescale Semiconductor, “MCF547X Family Integrated Microprocessor Product Brief”, Rev. 1.3, Sep. 2004, pp. 1-15.
Faraday Technology Corp.
Hsu Winston
Lamarre Guy
Trimmings John P.
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