Device scheme of HKMG gate-last process

Details Device scheme of HKMG gate-last process Device scheme of HKMG gate-last process

2009-08-06

2011-11-15

Picardat, Kevin M (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S183000, C438S233000, C438S259000, C438S261000, C438S275000, C438S279000, C438S591000

Reexamination Certificate

active

08058119

ABSTRACT:
The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.

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Chinese Patent Office, Office Action mailed Dec. 2, 2010; Application No. 200910168339.1, 7 pages.

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