Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-06-26
2007-06-26
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S733000, C324S607000, C341S120000
Reexamination Certificate
active
11231562
ABSTRACT:
An apparatus for testing an integrated circuit that includes analog nodes is disclosed. In one aspect, an integrated circuit comprises testing circuitry and core logic circuitry. A memory in the testing circuitry stores data identifying analog nodes in the core logic circuitry and tolerance values associated with the analog nodes. A condition checker compares actual test values with the associated tolerance values. A main control unit controls the testing circuitry and synchronizes testing of the core logic circuitry. In another aspect, the testing circuitry includes a host computer interface useful for communicating with a host computer. A data memory in the testing circuitry is used for storing diagnostic data. The contents of the data memory may then be uploaded to a host computer. Test stimuli may be transmitted to the integrated circuit from a location outside the integrated circuit to perform testing.
REFERENCES:
patent: 4503537 (1985-03-01), McAnney
patent: 5414365 (1995-05-01), Coggins et al.
patent: 5481471 (1996-01-01), Naglestad et al.
patent: 5568493 (1996-10-01), Morris
patent: 5577052 (1996-11-01), Morris
patent: 5659312 (1997-08-01), Sunter et al.
patent: 6005407 (1999-12-01), Arabi et al.
patent: 6202183 (2001-03-01), Ginetti et al.
patent: 6532561 (2003-03-01), Turnquist et al.
patent: 6536006 (2003-03-01), Sugamori
patent: 6560734 (2003-05-01), Whetsel
patent: 6687868 (2004-02-01), Furukawa et al.
Fluence Technology Inc., “BISTMaxx™ Product Catalog,” 38 p. (Sep. 2000).
Texas Instruments, “IEEE Std 1149.1 (JTAG) Testability Primer,” 146 p. (1997).
LogicVision, “LogicVision—PLL BIST,” 1 p. (downloaded from http://www.logicvision.com/products/pll.html on Apr. 10, 2001).
Chatterjee and Nagi, “Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial,”IEEE 10thInt'l Conference on VLSI Design, pp. 388-392.
Wey, “Mixed-Signal Circuit Testing—A Review,”Third Int'l Conference on Electronics, Circuits and Systems, pp. 1064-1067 (1996).
Lin et al., “Automatic BIST Design Tool for Mixed-Signal Circuits,”AUTOTESTCON '98: IEEE Systems Readiness Technology Conference, 97-102 (1998).
Lubaszewski et al., “Design of Self-Checking Fully Differential Circuits and Boards,”IEEE Transactions on VLSI Systems, vol. 8, No. 2, pp. 113-128 (Apr. 2000).
“IEEE Standard for a Mixed-Signal Test Bus,”IEEE Std. 1149.4, 84 pp. (2000).
“IEEE Standard Test Access Port and Boundary-Scan Architecture,”IEEE Std. 1149.1-1a, 172 pp. (1993).
Nicolaidis & Zorian, “Scaling Deeper to Submicron: On-Line Testing to the Rescue,”IEEE Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 1 p. (1999).
Milor, “A Tutorial Introduction to Research on Analog and Mixed-Signal Circuit Testing,”IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 45, No. 10, pp. 1389-1407 (Oct. 1998).
Klarquist & Sparkman, LLP
Lamarre Guy
Trimmings John P.
LandOfFree
Design for test of analog module systems does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Design for test of analog module systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design for test of analog module systems will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3864165