Defect and etch rate control in trench etch for dual...

Details Defect and etch rate control in trench etch for dual... Defect and etch rate control in trench etch for dual...

2001-09-06

2002-09-24

Christianson, Keith (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000, C438S706000, C438S790000

Reexamination Certificate

active

06455411

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of forming interconnect layers in integrated circuits and more specifically to dual damascene interconnect processes with Cu and low-k dielectrics.
BACKGROUND OF THE INVENTION
As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increase. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a conventional interconnect process, the aluminum (and any barrier metals) are deposited, patterned, and etched to form the interconnect lines. Then, an interlevel dielectric (ILD) is deposited and planarized. In a damascene process, the ILD is formed first. The ILD is then patterned and etched. The metal is then deposited over the structure and then chemically-mechanically polished to remove the metal from over the ILD, leaving metal interconnect lines. A metal etch is thereby avoided.
One prior art damascene process, a dual damascene process, is described with reference to
FIGS. 1A-E
. Referring to
FIG. 1A
, a silicon nitride layer
12
is deposited over a semiconductor body
10
. Semiconductor body
10
will have been processed through a first metal interconnect layer. A via level dielectric
14
is deposited over silicon nitride layer
12
. Via dielectric layer
14
comprises FSG (fluorine-doped silicate glass). Another silicon nitride layer
18
is deposited over via level dielectric
14
and a second, trench level dielectric
20
is deposited over silicon nitride layer
18
. A via
22
is then patterned and etched through the trench level dielectric
20
, silicon nitride layer
18
and via level dielectric
14
. Silicon nitride layer
12
is used as an etch-stop.
Referring to
FIG. 1B
, a spin-on organic barc (bottom anti-reflection coating)
24
is deposited to fill a portion of via
22
. The result is approximately 600 Å of barc over dielectric
20
and a thickness of ~2000-2500 Å inside the via
22
. Barc
24
protects via
22
during the subsequent trench etch. Next, the trench pattern
26
is formed on the structure as shown in FIG.
1
C. Trench pattern
26
exposes areas of trench level dielectric
20
(with about 600 Å of barc on top of dielectric
20
) where the metal interconnect lines are desired. Referring to
FIG. 1D
, the trench etch to remove portions of FSG layer
20
is performed. Oxide ridges
28
may undesirably form on the edges of via
22
. Pattern
26
is removed as shown in FIG.
1
E. Oxide ridges impair device reliability due to the fact that it is difficult to ensure that a metal barrier completely covers the oxide ridges.
Newer technologies are switching to even lower-k dielectrics such as organo-silicate glass (OSG) in place of FSG. Dual damascene processes for working with the newer dielectrics are needed.
SUMMARY OF THE INVENTION
A dual damascene process for low-k and ultra-low-k dielectrics is disclosed herein. After the via etch, a trench is etched using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N
2
/Ar ratio. The low N
2
/Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a high-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.
An advantage of the invention is providing a dual damascene process that avoids or minimizes the formation of via ridges while maintaining a high etch rate and good CD control.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.


REFERENCES:
patent: 6180540 (2001-01-01), Jang
patent: 6204192 (2001-03-01), Zhao et al.
patent: 6211092 (2001-04-01), Tang et al.
patent: 6232237 (2001-05-01), Tamaoka et al.
patent: 6284149 (2001-09-01), Li et al.
patent: 6316351 (2001-11-01), Chen et al.
patent: 6326296 (2001-12-01), Tsai et al.
patent: 6372634 (2002-04-01), Qiao et al.
patent: 2001/0008226 (2001-07-01), Hung et al.
patent: 2002/0038910 (2002-04-01), Inoue et al.

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