Common test logic for multiple operation modes

Details Common test logic for multiple operation modes Common test logic for multiple operation modes

2008-01-23

2010-06-08

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000, C714S733000

Reexamination Certificate

active

07734972

ABSTRACT:
In one embodiment, the present invention includes a processor having a plurality of logical units to perform operations on data. Each unit may include a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from input signals to the unit. In turn, each MISR may includes bit cells, each having a first cell to receive incoming data and controlled by a first clock signal, a second cell to receive an output of the first cell and controlled by a second clock signal, a mask cell to receive an output of the second cell and to generate a mask signal responsive to a mask clock signal, and a multiplexer coupled between the first and second cells. Other embodiments are described and claimed.

REFERENCES:
patent: 6009488 (1999-12-01), Kavipurapu
patent: 7028239 (2006-04-01), Jaber
patent: 7256055 (2007-08-01), Aghababazadeh et al.
patent: 7353440 (2008-04-01), Ohwada et al.
patent: 7647476 (2010-01-01), Mozak et al.
patent: 2008/0134180 (2008-06-01), Floyd
patent: 2008/0276144 (2008-11-01), Huben et al.

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