Circuit and method for a Vdd level memory sense amplifier

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S204000, C365S205000

Reexamination Certificate

active

07848166

ABSTRACT:
A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.

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patent: 2008/0159028 (2008-07-01), Choi
patent: 2008/0181038 (2008-07-01), Clinton
Tantawy, R., et al., “Performance Evaluation of CMOS Low Drop-Out Voltage Regulators,” 47thIEEE International Midwest Symposium on Circuits and Systems, Jul. 25-28, 2004, pp. I-141-I-144, vol. 1.
Maity, A., et al., “On-chip Voltage Regulator with Improved Transient Response,” IEEE Proceedings of the 18thInternational Conference on VLSI Design, Jan. 3-7, 2005, pp. 522-527.

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