Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Housing or package filled with solid or liquid electrically...
Reexamination Certificate
2007-06-12
2007-06-12
Zarneke, David A. (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Housing or package filled with solid or liquid electrically...
C257S778000, C257S787000, C257SE23124
Reexamination Certificate
active
10707683
ABSTRACT:
A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.
REFERENCES:
patent: 6339254 (2002-01-01), Venkateshwaran et al.
patent: 2003/0183946 (2003-10-01), Fukuda et al.
Chen Kai-Chi
Fukui Taro
Huang Shu-Chen
Lee Tzong-Ming
Li Hsun-Tien
Jianq Chyun IP Office
Matsushita Electric & Works Ltd.
Zarneke David A.
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