Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-03-08
2003-11-18
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S735000
Reexamination Certificate
active
06651202
ABSTRACT:
STATEMENTS REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
REFERENCE TO A MICROFICHE APPENDIX
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to testing of integrated circuits, and more particularly to a method for performing built-in self repair operations without the need to perform built-in self test.
2. Description of the Related Art
Improvements in semiconductor processes are making possible integrated circuits of increasing size and complexity. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems, including memories, can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuits (also referred to as “die” or “chips”) may use many functions that previously could not be implemented on a single die. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. However, due to the complex nature of today's integrated circuits and a concomitant sensitivity to variations in manufacturing processes, manufacturers are constantly confronted with new testing challenges.
Before manufacturers release integrated circuits for shipment, the devices typically undergo a variety of testing procedures. In ASIC devices incorporating integrated memories, for example, specific tests are performed to verify that each of the memory cells within the integrated memory array(s) is functioning properly. This testing is necessary because perfect yields are difficult to achieve. It is not uncommon for a certain percentage of unpackaged ASIC die to contain memory cells which fail testing processes, due largely to non-systemic manufacturing defects. Such manufacturing issues are likely to increase as process geometries continue to shrink and the density of memory cells increases. Even today, up to 100 Mbits or more of dynamic random access memory (DRAM), or several megabits of static random access memory (SRAM) or flash memory can be integrated onto a single integrated circuit.
A number of ASIC memory testing strategies have evolved, many of which involve use of an external memory tester or Automated Test Equipment (ATE). If memory is accessible from input/output (I/O) pins, either directly or by multiplexing, a hardware test mode can be utilized. In this mode, a production test system accesses the memory directly by writing to and reading from the memory bits. While this methodology does not use any chip area other than simple multiplexing circuitry, it is limited to on-chip memories and other circuitry accessible via I/O pins. Another drawback of this approach is that ATE capabilities are generally not available to end-users once the devices have been shipped, making it difficult to detect faults occurring after shipment.
If an embedded memory is buried deeply within an ASIC, built-in self-test (BIST) is often considered the most practical and efficient test methodology and is becoming increasing popular with semiconductor vendors. BIST allows timely testing of the memory with a reasonably high degree of fault coverage, without requiring complex external test equipment and large amounts of external access circuitry. With BIST, memory or logic circuitry can be tested at any time in the field. This capability offers some degree of continued fault protection.
BIST refers in general to any test technique in which test vectors are generated internal to an integrated circuit or ASIC. Test vectors are sequences of signals that are applied to integrated circuitry to determine if the integrated circuitry is performing as designed. BIST can be used to test memories located anywhere on the ASIC without requiring dedicated I/O pins, and can be used to test memory or logic circuitry every time power is applied to the ASIC, thereby allowing an ASIC to be easily tested after it has been incorporated in an end product. A number of software tools exist for automatically generating BIST circuitry, including RAMBIST Builder by LSI Logic of Milpitas, Calif. Such software produces area-efficient BIST circuitry for testing memories, and reduces time-to-market and test development costs.
In the BIST approach, a test pattern generator and test response analyzer are incorporated directly into the device to be tested. BIST operation is controlled by supplying an external clock and via use of a simple commencement protocol. BIST test results are typically compressed—usually to the level of “passed” or “failed”. At the end of a typical structured BIST test, or “run”, a simple pass/fail signal is asserted, indicating whether the device passed or failed the test. Intermediate pass/fail signals may also be provided, allowing individual memory locations or group of locations to be analyzed. Unlike external testing approaches, at-speed testing with BIST is readily achieved. BIST also alleviates the need for long and convoluted test vectors and may function as a surrogate for functional testing or scan testing. Since the BIST structures exist and remain active throughout the life of the device, BIST can be employed at the board or system level to yield reduced system testing costs, and to reduce field diagnosis and repair costs.
In addition to the aforementioned testing procedures, manufacturers use a number of techniques to repair faulty memories when feasible. Such techniques include bypassing defective cells using laser procedures and fused links that cause address redirection. However, such techniques are limited to one-time repair and require significant capital investment. Further, these techniques may leave integrated circuits useless if the repaired memories become defective after shipment from the manufacturing site—even where test equipment is available to end users, traditional field repairs have been expensive, time consuming, and largely impracticable.
In order to enhance the repair process, on-chip built-in self repair (BISR) circuitry for repairing faulty memory cells has evolved. BISR circuitry functions internal to the integrated circuit without detailed interaction with external test or repair equipment. In the typical BISR approach, suitable test algorithms developed and implemented in BIST or BIST-like circuitry. These test patterns may be capable of detecting stuck-at, stuck-open, bridging faults and retention faults during memory tests. Following execution of the test patterns, the BISR circuitry analyzes the BIST “signature” (results) and, in the event of detected faults, automatically reconfigures the defective memory utilizing redundant memory elements to replace the defective ones. A memory incorporating BISR is therefore defect-tolerant. The assignee of the present invention, LSI Logic Corporation, has addressed different methods of repairing faulty memory locations utilizing BIST and BISR circuitry, as disclosed in U.S. Pat. No. 5,764,878, entitled “BUILT-IN SELF REPAIR SYSTEM FOR EMBEDDED MEMORIES”, U.S. patent application No. 09/209,938, entitled “REDUNDANCY ANALYSIS FOR EMBEDDED MEMORIES WITH BUILT-IN SELF TEST AND BUILT-IN SELF REPAIR” filed Dec. 11, 1998, now U.S. Pat. No. 6,067262, and U.S. patent application No. 09/209,996, entitled “TESTING SCHEME FOR EMBEDDED MEMORIES USING BISR AND FUSE ID” filed Dec. 11, 1998, now U.S. Pat. No. 6,367,042, all of which are hereby incorporated by reference as if set forth in their entirety.
BISR compliments BIST because it takes advantage of on-chip processing capabilities to re-route bad memory bits rather than using an expensive and slow laser burning process to replace faulty memory locations. Some BISR circuitry is capable of repairing the faulty memory locations by redirecting the original address locations of faulty memory lines to the mapped addressed locations of the redundant columns and rows. Options for repair include either row and column replacement when a bad bit is found in a particular row or column.
An important feature of any integrated circuit
Akin Gump Strauss Hauer & Feld & LLP
LSI Logic Corporation
Ton David
LandOfFree
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