4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Robert Lee Ayers, Sr.

Inventor

Rate now
  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Inventor

active

Boundary scan apparatus and interconnect test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Boundary scan apparatus and interconnect test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Boundary scan apparatus and interconnect test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

No associations

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Robert Lee Ayers, Sr. does not yet have a rating. At this time, there are no reviews or comments for this inventor.

If you have personal experience with Robert Lee Ayers, Sr., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Robert Lee Ayers, Sr. will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-P-2961840

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.

Canada

 Charities
 Companies
 MP Candidates
 Patents
 Employee Salary Disclosure

World

 Places of the World
 Scientific Papers

United States

 Banks
 Companies
 Counties
 Patents
 Employee Salary Disclosure