Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2002-03-25
2003-04-29
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S692000, C257S693000, C257S696000, C438S109000, C438S118000
Reexamination Certificate
active
06555918
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a technology that can be effectively adapted to a semiconductor device in which two semiconductor chips are stacked one upon the other and are molded with a resin.
In a semiconductor device in which a semiconductor chip constituting a DRAM (dynamic random access memory) is molded with a resin, there has been employed an LOC (lead on chip) structure which can be applied to a semiconductor chip of even a large size, thereby eliminating die pads (also referred to as tabs) of the lead frame. A semiconductor device employing a LOC structure has been disclosed in, for example, Japanese Patent Laid-Open No. 2-246125/1990 (laid open on Oct. 1, 1990).
In order to accomplish a large capacity, there has been developed a semiconductor device employing a LOC structure; i.e., in which two semiconductor chips constituting DRAMs of the same capacity are stacked one upon the other and are molded with the same resin.
The above semiconductor device is constituted by a resin mold, two semiconductor chips positioned inside the resin mold and having external terminals on the circuit-forming surfaces thereof, which are the front surfaces out of the front surfaces and the back surfaces, and leads extending from the inside to the outside of the resin mold. The two semiconductor chips are stacked one upon the other in a state where the circuit-forming surfaces are opposed to each other. Each lead has two branch leads branched in the up-and-down direction in the resin mold. The one branch lead is adhered and secured, via an insulating film, to the circuit-forming surface of the one semiconductor chip and is electrically connected, via an electrically conductive wire, to an external terminal of the circuit-forming surface. The other branch lead is adhered and secured, via an insulating film, to the circuit-forming surface of the other semiconductor chip and is electrically connected, via an electrically conductive wire, to an external terminal of the circuit-forming surface.
The two branch leads are constituted by separate members. The one branch lead is led to the outside of the resin mold and is integrated with an external lead formed in a predetermined shape. The other branch lead is joined to the one branch lead in the resin mold and is electrically and mechanically connected thereto. That is, the lead extending from the inside to the outside of the resin mold is constituted by an external lead led to the outside of the resin mold, the one branch lead integral with the external lead, and the other branch lead joined to the one branch lead.
The above-mentioned semiconductor device has been disclosed in, for example, Japanese Patent Laid-Open No. 7-58281/1995 (laid open on Mar. 3, 1995).
SUMMARY OF THE INVENTION
In the above-mentioned semiconductor device, the two semiconductor chips are stacked one upon the other in a state where the circuit-forming surfaces are opposed to each other. Therefore, the two branch leads branched in the up-and-down direction are present between the two semiconductor chips in the resin mold. The two branch leads are connected, through wires, to the surfaces (bonding surfaces) opposed to each other and are, hence, spaced away from each other. Therefore, the gap between the two semiconductor chips is widened by an amount corresponding to the gap (distance) between the two branch leads, resulting in an increase in the thickness of the resin mold and an increase in the thickness of the semiconductor device.
Furthermore, the two branch leads are present between the two semiconductor chips. Therefore, a stray capacitance (chip-lead capacitance) produced relative to the one semiconductor chip and a stray capacitance (chip-lead capacitance) produced relative to the other semiconductor chip, are added to the two branch leads. Accordingly, an increased stray capacitance is added to a lead that is extending from the inside to the outside of the resin mold, resulting in a decrease in the propagation speed of signals through the lead and a decrease in the electric characteristics of the semiconductor device.
An object of the present invention is to provide technology capable of decreasing the thickness of a semiconductor device.
Another object of the present invention is to provide a technology capable of improving the electric characteristics of a semiconductor device.
The above and other objects as well as novel features of the present invention will become obvious from the description providied in this specification and from the accompanying drawings.
Briefly described below are representative aspects of the invention disclosed in this application.
(1) A semiconductor device comprising:
a resin mold;
two semiconductor chips positioned inside said resin mold and having external terminals formed on the front surfaces (circuit-forming surfaces) out of the front surfaces and the back surfaces thereof; and
leads extending from the inside to the outside of said resin mold; wherein,
each of said leads is branched into two branch leads in at least said resin mold;
one branch lead is secured to the surface of said one semiconductor chip and is electrically connected to an external terminal on the surface thereof;
the other branch lead is secured to the surface of said other semiconductor chip and is electrically connected to an external terminal on the surface thereof; and
said two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
The one branch lead is electrically connected to an external terminal on the surface of said one semiconductor chip through an electrically conductive wire, and the other branch lead is electrically connected to an external terminal on the surface of said other semiconductor chip through an electrically conductive wire.
Moreover, the one branch lead is adhered and secured to the surface of said one semiconductor chip via an insulating film or an insulating adhesive agent, and the other branch lead is adhered and secured to the surface of said other semiconductor chip via an insulating film or an insulating adhesive agent.
(2) In the semiconductor device described in item (1) above, the back surfaces of the two semiconductor chips are in contact with each other.
(3) In the semiconductor device described in item (1) above, a portion of the one branch lead opposed to the surface of said one semiconductor chip has a thickness smaller than that of the other portions, and a portion of the other branch lead opposed to the surface of said other semiconductor chip has a thickness smaller than that of the other portions.
(4) A semiconductor device comprising:
a resin mold;
two semiconductor chips positioned inside said resin mold and having a plurality of external terminals formed on the front surfaces out of the front surfaces and the back surfaces thereof; and
first leads and second leads extending from the inside to the outside of said resin mold; wherein,
said two semiconductor chips are stacked one upon the other in a state where their back surfaces are opposed to each other;
said first leads are electrically connected to the external terminals of said two semiconductor chips;
said second leads are electrically connected to the external terminals of either one of said two semiconductor chips;
each said first leads is branched into two branch leads in said resin mold;
said one branch lead is secured to the surface of said one semiconductor chip out of said two semiconductor chips and is electrically connected to an external terminal formed on the surface thereof through an electrically conductive wire;
the other branch lead is secured to the surface of the other semiconductor chip out of said two semiconductor chips and is electrically connected to an external terminal formed on the surface thereof through an electrically conductive wire; and
said second leads are secured to the surface of either one of said two semiconductor chips and are electrically connected to external terminals formed on the surface thereof
Kawamura Masayasu
Masuda Masachika
Nishizawa Hirotaka
Sugano Toshio
Sugiyama Michiaki
Berezny Nema
Jr. Carl Whitehead
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