Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-01-09
2007-01-09
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S033000
Reexamination Certificate
active
10678975
ABSTRACT:
An apparatus for selecting test patterns in accordance with an embodiment of the present invention has a first test pattern selecting module configured to define selected test patterns and unselected test patterns, a fault simulation module configured to simulate whether test patterns detect faults, a weighting module configured to add a weight to each of the first undetected faults, a fault sampling module configured to extract second undetected faults from the first undetected faults to which the added weights are given, and a second test pattern selecting module configured to extract additionally selected test patterns based on the added weight.
REFERENCES:
patent: 4769817 (1988-09-01), Krohn et al.
patent: 5414716 (1995-05-01), Bershteyn
patent: 5771243 (1998-06-01), Lee et al.
patent: 6308293 (2001-10-01), Shimono
patent: 6567946 (2003-05-01), Nozuyama
patent: 2001/0027539 (2001-10-01), Nozuyama
patent: 401088266 (1989-04-01), None
patent: 06-201791 (1994-07-01), None
patent: 07-055895 (1995-03-01), None
patent: 09-145800 (1997-06-01), None
patent: 09-264938 (1997-07-01), None
patent: 11-052030 (1999-02-01), None
patent: 2000-276500 (2000-10-01), None
patent: 2001-273160 (2001-10-01), None
The Official Action Letter issued on Mar. 7, 2006 regarding the counterpart Japanese Patent Application No. 2002-291442.
Y. Nozuyama, et al., “A Method For Estimating And Enhancing Test Quality Using Layout Information —A Basic Method and A Few Examples (Bridge Fault Iddq Test, Weighted Stuck-at Fault Coverage)-”, Technical Report of IEICE (Japan), vol. CPM 2002-152, ICD2002-197, The Institute Of Electronics, Information And Communications Engineers), (Jan. 2003).
DLA Piper (US) LLP
Kabushiki Kaisha Toshiba
Lamarre Guy
Trimmings John P.
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