Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-07-03
2007-07-03
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C708S232000, C713S401000, C327S269000
Reexamination Certificate
active
10906448
ABSTRACT:
An apparatus for performing stuck fault testings within an integrated circuit is disclosed. A delay chain structure includes a first select register, a second select register, a decoder and a chain of multiplexors. With a set of select signals, the first select register generates a set of true encoded select signals, and the second select register generates a set of complement encoded select signals. Coupled to the first and second select registers, the decoder decodes the set of true encoded select signals and the set of complement encoded signals for controlling the chain of multiplexors. Each multiplexor within the chain of multiplexors is connected to one of the outputs of the decoder. The chain of multiplexors generates a single output value based on the set of select signals.
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patent: 6380785 (2002-04-01), Fisher
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“74VHCT138A 3-to-8 Decoder/Demultiplexer”, Fairchild Semiconductor Corp., at www.fairchildsemi.com, 1999, DS500014.prf.
Bialas, Jr. John Stanley
Kilmoyer Ralph D.
Dillon & Yudell LLP
Lamarre Guy
LeStrange Michael J.
Trimmings John P.
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