Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2002-06-14
2004-03-30
Cho, James H (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S030000
Reexamination Certificate
active
06714038
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2001-42329 filed on Jul. 13, 2001.
BACKGROUND
1. Technical Field
The present invention relates to an apparatus and method for controlling a semiconductor memory device, and more particularly, to an apparatus and method for controlling the operation of an input termination of a semiconductor memory device, so that the input termination can be turned off during a testing operation to detect and analyze defects, functions, and reliability of the semiconductor device.
2. Description of Related Art
Typically, an ultrahigh-speed semiconductor memory device having a data transmission rate of greater than 1 Gbps will comprise an input termination. The input termination is used to reduce the skew on a signal transmission line that is caused by reflection waves due to impedance mismatches between sources during a reading or writing operation.
For instance, when a cache memory (such as SRAM) directly transfers and receives data to and from a central processing unit (CPU), if there is an impedance mismatch between the transmission line and the receiving terminal of the SRAM, the signal transmitted to the SRAM will be skewed. In other words, in case of an external input signal having a low frequency, there is a time gap between the falling time of a current input signal and the rising time of a next input signal. In case of an external input signal having a high frequency, the falling time of a current input signal will overlap with the rising time of a next input signal before the falling time of the current input signal completely ends. Thus, a skewed signal is transmitted from the CPU through the transmission line to the SRAM.
FIG. 1
is a circuit diagram of a conventional impedance match control circuit of a semiconductor memory device. The impedance match control circuit comprises an input terminal P
1
, an input termination
10
, and a normal receiver
12
for receiving an input signal through the input terminal circuit
10
.
The input termination
10
, which comprises resistors R
1
and R
2
serially connected between a supply voltage VDD and a ground voltage, is used to match the impedance of the input terminal P
1
and the transmission line connected to the input terminal P
1
, thereby reducing skew of the input signal.
However, since the input termination
10
generates an excessive amount of current through the two resistors R
1
and R
2
in response to the supply voltage VDD, it is difficult to detect leakage current (that may be caused by, e.g., a manufacturing defect) during the transformation of the received input signal by the normal receiver
12
, which results in an excess amount of current flow in the input termination.
Therefore, a need exists for controlling the input termination in a manner that would enable detection of leakage current. Further, it would be advantageous to be able to turn the input termination off to allow one to test a semiconductor memory device within an allowable current range of test equipment.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for controlling the operation of an input termination of a semiconductor memory device, so that the input termination can be turned off during a testing operation of a semiconductor device to detect and analyze defects, functions and reliability of the semiconductor device.
According to one aspect of the present invention, an apparatus for controlling an input termination of a semiconductor memory device comprises an input termination circuit for matching an impedance of a transmission line, a control circuit for processing test commands and outputting control signals in response to said processing, and a switching circuit for selectively turning on/off the input termination circuit in response to the control signals output from the control circuit.
According to another aspect of the present invention, an apparatus for controlling an input termination of a semiconductor memory device, comprises a pad for receiving a first control signal to control an input termination circuit, and a switching circuit that selectively turns on/off the input termination circuit in response to the first control signal.
According to yet another aspect of the present invention, a semiconductor memory device, comprises an input termination circuit for matching an impedance of a transmission line connected to the semiconductor device, and a pad for receiving a control signal that one of activates and deactivates the input termination circuit, wherein the input termination circuit is deactivated to prevent leakage current from flowing in the input termination circuit.
According to further aspect of the present invention, a method for controlling an input termination of a semiconductor memory device, comprises the steps of outputting a control signal to deactivate an input termination, when a testing procedure is to be performed for the semiconductor device, and deactivating a plurality of switches to electrically isolate the input termination, and thus, prevent leakage current from flowing in the input termination.
These and other aspects, features, and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in conjunction with the accompanying figures.
REFERENCES:
patent: 5596757 (1997-01-01), Smith
patent: 5731711 (1998-03-01), Gabara
patent: 6054881 (2000-04-01), Stoenner
patent: 6313659 (2001-11-01), Bosnyak et al.
patent: 05083114 (1993-04-01), None
Lee Byong-Kwon
Lee Kwang-Jin
F. Chau & Associates LLC
Samsung Electronics Co,. Ltd.
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