Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-11-07
2006-11-07
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S201000, C714S719000, C714S733000, C714S030000
Reexamination Certificate
active
07134063
ABSTRACT:
An apparatus for testing an on-chip ROM and a method thereof are provided. By embedding the on-chip ROM test apparatus in a semiconductor chip and externally providing only minimal information, the apparatus and the method can prevent the possible exposure of ROM data stored in the ROM. Also, according to the apparatus and method, information related to the ROM address at which an error occurred can be provided together with the test result and by feeding the ROM address information back to the manufacturing process, product yield can be improved.
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Cho Sang-Yeun
Kim Yong-chun
Lamarre Guy
Mills & Onello LLP
Trimmings John P.
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