Apparatus and method for testing on-chip ROM

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C365S201000, C714S719000, C714S733000, C714S030000

Reexamination Certificate

active

07134063

ABSTRACT:
An apparatus for testing an on-chip ROM and a method thereof are provided. By embedding the on-chip ROM test apparatus in a semiconductor chip and externally providing only minimal information, the apparatus and the method can prevent the possible exposure of ROM data stored in the ROM. Also, according to the apparatus and method, information related to the ROM address at which an error occurred can be provided together with the test result and by feeding the ROM address information back to the manufacturing process, product yield can be improved.

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Van Wauwe et al., “A Cost Effective Way to Test Embedded RAM and ROM”, Sep. 17-21, 1990, IEEE ASIC Seminar and Exhibit, 1990, pp. 14/8.1-14/8.4.

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