Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-01-23
2007-01-23
Ton, David (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S819000, C365S201000
Reexamination Certificate
active
10853573
ABSTRACT:
An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.
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Ayres Scott L.
Brown David R.
Cooper Chris
Gatzemeier Scott N.
Giam Siang Tian
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
Ton David
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