Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2007-12-25
2007-12-25
Lamarre, Guy (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
10926932
ABSTRACT:
A method for generating a parity check matrix of a block LDPC code is disclosed. The parity check matrix includes an information part corresponding to an information word and a first parity part and a second parity part each corresponding to a parity. The method includes determining a size of the parity check matrix based on a coding rate applied when coding the information word with the block LDPC code, and a codeword length; dividing a parity check matrix with the determined size into a predetermined number of blocks; classifying the blocks into blocks corresponding to the information part, blocks corresponding to the first parity part, and blocks corresponding to the second parity part; arranging permutation matrixes in predetermined blocks from among the blocks classified as the first parity part, and arranging identity matrixes in a full lower triangular form in predetermined blocks from among the blocks classified as the second parity part; and arranging the permutation matrixes in the blocks classified as the information part such that a minimum cycle length is maximized and weight values are irregular on a factor graph of the block LDPC code.
REFERENCES:
patent: 6539367 (2003-03-01), Blanksby et al.
patent: 6895547 (2005-05-01), Eleftheriou et al.
patent: 7000174 (2006-02-01), Mantha et al.
patent: 7000177 (2006-02-01), Wu et al.
patent: 7072417 (2006-07-01), Burd et al.
patent: 7139959 (2006-11-01), Hocevar
patent: 2002/0181569 (2002-12-01), Goldstein et al.
patent: 2003/0033575 (2003-02-01), Richardson et al.
patent: 2003/0037298 (2003-02-01), Eleftheriou et al.
patent: 2004/0034828 (2004-02-01), Hocevar
patent: 2004/0148560 (2004-07-01), Hocevar
patent: 1 093 231 (2001-04-01), None
patent: 2004-266463 (2004-09-01), None
Echard et al., The Extended Irregular Π-Rotation LDPC Codes, IEEE Communications Letters, vol. 7, No. 5, May 2003, pp. 230-232.
Yeo et al., Architectures and Implementations of Low-Density Parity Check Decoding Algorithms, 2002 Midwest Symposium on Circuits and Systems, Aug. 4, 2002.
Zhang et al., An FPGA Implementation of (3,6)-Regular Low-Density Parity Check Code Decoder, EURASIP Journal of Applied Signal Processing, Aug. 4, 2002.
Richardson et al., Efficient Encoding of Low-Density Parity-Check Codes, IEEE Transactions on Information Theory, Feb. 2, 2001.
Eleftheriou et al., Low-Density Parity-Check Codes for Digital Subscriber Lines, 2002 IEEE International Conference on Communications, Apr. 28, 2004.
Mittelholzer et al., Efficient Encoding and Minimum Distance Bounds of Reed-Solomon-Type Array Codes, 2002 IEEE International Symposium on Information Theory, Jun. 30, 2002.
Jon-Lark Kim, “Explicit Construction of Families of LDPC Codes with Girth at Least Six”, Oct. 2002.
John L. Fan, “Array Codes as Low-Density Parity-Check Codes”, Sep. 2000.
Rich Echard et al., “The Π-Rotation Low-Density Parity Check Codes”, Nov. 25, 2001.
Dale E. Hocevar, “Efficient Encoding for a Family of Quasi-Cyclic LDPC Codes”, Dec. 1, 2003.
Jeong Hong-Sil
Kim Jae-Yoel
Kyung Gyu-Bum
Myung Se-Ho
Park Sung-Eun
Lamarre Guy
Rizk Sam
Samsung Electronics Co,. Ltd.
The Farrell Law Firm P.C.
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