Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-07-02
2001-03-13
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C324S500000, C326S016000
Reexamination Certificate
active
06202183
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the testing of analog circuitry and more specifically to an improved system and method for ensuring the testability of analog cells embedded in mixed signal products.
2. Description of the Prior Art
The requirements of modem electronic circuits, particularly electronic circuits typically implemented as integrated circuits (IC's) such as computer processors, signal converters, modems and control circuits, dictate the use of “mixed signal” design solutions in which one or more analog cells is “embedded” within the digital modules which make up the remainder of the chip. This remainder of the IC chip which surrounds and couples to the embedded analog cells is often called the “core logic” portion of the chip. Mixed signal implementations greatly simplify overall system design.
Mixed signal products do, however, present special testing problems in the manufacturing process. These problems arise because the complete and accurate test of an embedded analog cell requires a direct access to the inputs and outputs of the cell. This access is difficult to obtain since the analog cell is embedded, which means that all of these inputs and outputs internally interconnect to other circuit modules on the IC, and are therefore not accessible via the normal interconnection points (bonding pads) of the IC.
One prior art approach which has been used to obtain direct access to the inputs and the outputs of an embedded analog cell is to make use of multiplexed (MUXed) pads. In this method, called “MUX isolation,” external pads of the IC chip are MUXed to establish either the interconnection required for the normal functioning of the IC chip, or, to an input or output of the analog cell to provide the direct access required for analog cell testability. One variation of this approach is to use “complete MUX isolation” in which MUX's are added in front of each digital input of the analog cell and also to provide access to all outputs. Although this approach provides access directly to the inputs and outputs of a given analog cell, the fact that a MUX must be added to the IC chip layout for all inputs and outputs of each of the analog cells present on the IC chip, and the fact that many analog cells are typically required to accomplish the complex internal functions of a mixed signal IC chip results in excessively large numbers of MUXed circuit pads with complex signal path routings on the IC chip. Another variation of this approach is to use “partial MUX isolation” in which MUX's are added for dynamic signals only (i.e. static configurations stored in product registers in the core logic) while direct access is provided for the analog data inputs and outputs. Disadvantages of this variation are that a long and deep test program customized for each product is required, and complete testability is not ensured.
Another problem which must be solved in connection with the testing of analog cells is to provide some kind of signal or indication that the chip is in an “analog test mode.” It is highly desirable to avoid having to dedicate any pin to the test of the chip even for selecting a test mode. One solution to avoid that need would be to “program” the chip by means of several initialization test vectors, but this approach has the disadvantage that analog testing is now dependent on information, whereas the best possible condition for effective testing is that it be independent of any “knowledge” of the core logic.
It is therefore clear that the problems or disadvantages of prior solutions include: (1) they involve huge numbers of MUXed pins and routing for complex cells; (2) they require a very complex test board: (3) they require initialization vectors or dedicated pins or both to control the MUX's; and (4) they make it difficult or impossible to verify testability in the case of multiple or complex analog cells.
As a result of the above-described problems and disadvantages, there exists a need for an improved and simplified system and method which ensures the testability of the embedded analog cells of a mixed signal product which is completely independent of the core logic of that product.
OBJECTS OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC.
It is a further object of this invention to provide an improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC wherein the testability is completely independent of the core logic of that IC.
It is a further object of this invention to provide an improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC wherein the testability is completely independent of the core logic of that IC and wherein the system and method do not require the dedication of any pin solely for the purpose of testing that IC.
It is another object of this invention to provide an improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC wherein the testability is completely independent of the core logic of that IC, wherein the system and method do not require the dedication of any pin solely for the purpose of testing that IC, and wherein the system and method incorporate a simplified test access configuration to streamline the IC chip layout and reduce the number of MUXed pins required
It is a further object of this invention to provide an improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC wherein the testability is completely independent of the core logic of that IC, wherein the system and method do not require the dedication of any pin solely for the purpose of testing that IC, and wherein the system and method incorporate a simplified test access configuration to streamline the IC chip layout and reduce the number of MUXed pins required, and wherein the system and method allows easy generation of test programs that can be applied to each analog cell tested.
It is still a further object of this invention to provide an improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC wherein the testability is completely independent of the core logic of that IC, which does not require the dedication of any pin solely for the purpose of testing that IC, wherein the system and method incorporate a simplified test access configuration to streamline the IC chip layout and reduce the number of MUXed pins required, wherein the system and method allows easy generation of test programs that can be applied to each analog cell tested, and wherein the system and method provides for the combination of these individual cell test programs to provide an overall test program which tests all analog cells present in the IC.
SUMMARY OF THE INVENTION
According to the foregoing objectives, this invention describes an improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC wherein the testability is completely independent of the core logic of that IC, wherein the system and method incorporates a simplified test access configuration to streamline the IC chip layout and reduce the number of MUXed pins required, wherein the system and method allows easy generation of test programs that can be applied to each analog cell tested, and wherein the system and method provides for the combination of these individual cell test programs to provide an overall test program which tests all analog cells present in the IC.
REFERENCES:
patent: 5404358 (1995-04-01), Russell
patent: 5535331 (1996-07-01), Swoboda et al.
patent: 5568493 (1996-10-01), Morris
patent: 5887001 (1999-03-01), Russell
patent: 0570067 A2 (1993-05-01), None
Liu, et al. (Mixed Signal Testing of Analog Components on Printed Circuit Boards. IEEE, 1997).
Lofstrom (A Demonstration IC for the P1149.4 Mixed Signal Test Standard. IEEE, 1996).
Starzyk, et al. (An O
Ginetti Bernard
Granzow Olaf
Zotier Christian
Cady Albert De
Lamarre Guy
Philips Semiconductors Inc.
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