Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-07
2002-09-10
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S688000
Reexamination Certificate
active
06448173
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to aluminum-based metallizations for integrated circuits. More particularly, this invention relates to a process of forming aluminum-based metallizations that exhibit improved life as a result of being less prone to electromigration.
2. Description of the Prior Art
Aluminum conductors (lines) are widely used as metal interconnects between active devices of semiconductor microcircuits. Although most aluminum interconnects in current integrated circuits (ICs) are formed by reactive ion etching (RIE) of aluminum deposited by physical vapor deposition (PVD), there has been much recent interest in forming aluminum interconnects through the use of damascene processes. As known in the art, while RIE techniques entail depositing and then patterning metal, damascene processes generally entail etching a submicron trench in a dielectric material (e.g., SiO
2
), and then filling the trench with a conductive material, such as aluminum, copper or tungsten. Excess conductive material is removed from the surface of the dielectric material by chemical-mechanical polishing (CMP) to produce a planar surface with a conductive line embedded in the dielectric material. Dual damascene involves simultaneously etching and filling a trench and one or more interlevel vias with a conductive material to form a conductive line and vias embedded in the dielectric material. The conductive material is again planarized by CMP to produce a planar surface on the embedded conductive line and vias.
Although a relatively more mature technique for IC interconnects, metal RIE techniques are becoming more difficult for a number of reasons, including higher aspect ratios for metal etching and oxide gap fill, as well as smaller overlay tolerances and the difficulty of etching aluminum alloys (especially Al-Cu alloys). Dual damascene processes avoid some of these problems, and offer a potential for lower cost by eliminating the use of tungsten studs as the via material. Of course, the lower cost made possible by a dual damascene process can only be realized if high yielding processes are developed for via and trench patterning, high aspect ratio metal fill, and chemical mechanical polishing of aluminum. An important consideration in this comparison is the electromigration properties of aluminum lines formed by the two methods. Aluminum lines are known to be subject to deterioration from electromigration, which is generally the movement of atoms caused by the interaction between electrons and ions in the presence of an electric current. In multilayered interconnections, a typical mode of failure from electromigration within an aluminum line is an excessive resistance increase due to the depletion of aluminum atoms from the cathode end and accumulation of aluminum atoms at the anode end. Enriching the grain boundaries and external interfaces of an aluminum line with copper has been employed to improve the electromigration resistance of aluminum lines by retarding aluminum diffusion.
A diffusion barrier formed along the external interfaces of an aluminum line has also been reported to reduce aluminum electromigration by inducing a stress gradient that, once sufficiently large as a result of the accumulation of aluminum atoms at the anode end of the line, opposes the electromigration driving force for aluminum migration toward the anode end. Examples of known diffusion barriers include a titanium layer alone or in combination with a titanium nitride layer, both typically deposited by physical vapor deposition (PVD). In short interconnections, this stress gradient causes the resistance increase to saturate with time, or otherwise reach some maximum value. This resistance change at saturation is known to depend on current density (j) and line length (L), such that the current density and line length product (jL) has been used as a parameter for assessing this phenomenon.
In the case of interconnections patterned by RIE techniques and terminated by tungsten studs, resistance saturation effects are most evident for line lengths of about 100 micrometers and less, with the result that relatively low saturation resistances tend to occur even with relatively high current densities. A critical current density x line length product (jL) of as low as 1020 A/cm has been reported for RIE aluminum interconnects, above which excessive resistance increases occur. However, for line lengths greater than 100 micrometers, the critical current density x line length parameter does not apply, and current densities must be maintained at significantly lower levels in order to yield resistance saturation levels comparable to those exhibited by lines shorter than 100 micrometers. For example, current densities (j) above about 2 MA/cm
2
can cause an excessive saturation resistance in a RIE aluminum line having a length of 100 micrometers or more.
Another apparent factor in electromigration through RIE interconnects is the fiber texture of the metal line. As known in the art, texture is the orientation (crystallographic) of the polycrystalline grains in the metal line, and describes how similar the orientations are. Fiber texture is typically found in thin films since the orientation of the grains is symmetric about the film normal. Metal RIE structures having randomly textured lines generally have shorter electromigration lives than those that are strongly textured. There is evidence that a correlation exists between a pronounced texture of the metal line grains and the formation of undesirable aluminum intermetallics, such as TiAl
3
that form as a reaction product of an aluminum line and a titanium diffusion barrier.
In the comparison of the electromigration properties of RIE and damascene lines, previous studies have provided seemingly contradictory results. Some research has concluded that lines formed by damascene processes have a fundamentally improved electromigration performance over RIE lines, while other research suggests that in some cases metal lines formed by RIE can outperform the electromigration characteristics of metal lines formed by dual damascene. Nonetheless, occurrence of the saturation resistance phenomenon in RIE aluminum lines is typically limited to line lengths of less than 100 micrometers. Therefore, it would be desirable if a metallization scheme were available that reduces the resistance saturation level or totally suppressed electromigration in aluminum lines having lengths greater than 100 micrometers.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process of this invention produces aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The invention evidences that the electromigration lifetime of a dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. However, the dual damascene process of this invention has been shown to provide electromigration reliability that is far better than any previously reported work for aluminum RIE interconnects. In one example, a current density as high as 2.5 MA/cm
2
is necessary in damascene aluminum lines with lengths of 200 micrometers to induce a statistically relevant number of fails due to electromigration.
According to this invention, a dual damascene technique is employed to produce a metal line that interconnects two electrically-conductive regions spaced laterally apart, such as metallizations in other levels of a multilayered circuit. The technique entails forming vias that extend through a dielectric material
Clevenger Lawrence Alfred
Filippi Ronald Gene
Gambino Jeffrey Peter
Gignac Lynne Marie
Hu Chao-Kun
Chaudhuri Olik
Hartman Domenica N. S.
Hartman Gary M.
International Business Machines - Corporation
Kielin Erik
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