Alignment system for planar charge trapping dielectric...

Details Alignment system for planar charge trapping dielectric... Alignment system for planar charge trapping dielectric...

2003-03-21

2003-12-23

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S401000

Reexamination Certificate

active

06667212

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to flash memory cell devices and more specifically, to improvements in planar charge trapping dielectric memory cell structures or improved alignment between lithography processes.
BACKGROUND OF THE INVENTION
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO
2
), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate are a channel region positioned below the vertical stack and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Si—SiO
2
energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the Si—SiO
2
interface under the influence of the control gate electrical field and gain sufficient energy to cross the barrier.
Once programmed, the negative charge on the floating gate increases the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate. During a “read” of the memory cell, the magnitude of the current flowing between the source and drain at a predetermined control gate voltage indicates whether the flash cell is programmed.
More recently a charge trapping dielectric memory cell structure that includes bit line oxides has been developed.
FIG. 1
a
represents a cross section of a portion of a row of such charge trapping dielectric memory cells (e.g. cells
10
a
and
10
b
). The cells
10
a
and
10
b
are fabricated on a semiconductor substrate
12
. Each cell
10
is characterized by a vertical stack of an insulating tunnel layer
14
a charge trapping dielectric layer
20
a
,
20
b
, and a top dielectric layer
22
a
,
22
b
formed over channel regions
24
a
,
24
b
of the substrate
12
. Such stack may be referred to as an ONO stack because the insulating tunnel layer
14
and the top dielectric layer
22
are typically an oxide while the center charge trapping dielectric layer
20
is typically a nitride compound. The channel regions
24
are separated from each other, and defined by, bitline implants
18
a
,
18
b
, and
18
c
within the substrate
12
. The ONO stacks are separated from each other, and defined by bit line oxide regions
16
a
,
16
b
, and
16
c
which are areas of the tunnel dielectric layer
14
above the bit line implants
18
that are thicker than the areas of the tunnel dielectric layer
14
that are over the channel regions
24
.
Above the ONO stacks are a plurality of spaced apart polysilicon word lines
26
that are perpendicular to the bit line implants
18
. Each word line is positioned above the top dielectric layer
22
of all cells within a row.
Similar to the floating gate device, the charge trapping dielectric memory cell
10
is programmed by inducing hot electron injection from the channel region
24
to the nitride layer
20
to create a non volatile negative charge within charge traps existing in the nitride layer
20
. Again, hot electron injection can be achieved by applying a drain-to-source bias (e.g. bit line
18
b
to bit line
18
a
bias for programming cell
10
a
) along with a high positive voltage on the polysilicon word line
26
which forms a control gate over the cell
10
a
. The high voltage on the word line
26
inverts the channel region
24
a
while the drain-to-source bias accelerates electrons towards the drain bitline
18
b
. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Si—SiO
2
energy barrier between the channel region
24
and the tunnel oxide layer
14
. While the electrons are accelerated towards the drain bitline
18
b
, those electrons which collide with the crystalline lattice are re-directed towards the Si—SiO
2
interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier.
Because the charge trapping layer
20
stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a charge storage region that is close to the drain region bit line to which the positive voltage was applied. As such, the charge trapping dielectric memory device can be used to store two bits of data, one near each of the bit lines of each cell.
The array is typically fabricated by first applying the ONO layer to the top surface of the substrate, etching back the ONO layer to the top surface of the substrate in the bit line regions, implanting the bit line regions, oxidizing the bit line regions to form the bit line oxides, and then applying the word lines to the top of the remaining ONO layer and the bit line oxides.
It should be appreciated that the height variations caused by the bit line oxides within the etched away portions of the ONO layer modulate reflected alignment illumination such that a lithography stepper may use an optical alignment system to properly align the various masks used during fabrication.
FIG. 1
b
represents a cross section of a portion of a row of charge trapping dielectric memory cells (e.g. cells
30
a
and
30
b
) with a planar structure. Cells
30
a
and
30
b
are fabricated on a semiconductor substrate
32
. Positioned over the semiconductor substrate
32
is a vertical stack of an insulating tunnel layer
34
a charge trapping dielectric layer
38
, and a top dielectric layer
40
positioned over the substrate
32
.
Within the substrate are a plurality of parallel, and spaced apart, bit line implants
36
a
,
36
b
, and
36
c
which define a plurality of channel regions
44
a
,
44
b
, each of which is between adjacent bit line implants. Above the top dielectric layer
40
are a plurality of parallel, spaced apart, polysilicon word lines which are perpendicular to the bit line implants
36
and the channel regions
44
. Each dielectric memory cell is defined by an intersection of a word line
42
and a channel region
44
.
A recognized advantage of the planar structure shown in
FIG. 1
b
over the bit line oxide structure depicted in
FIG. 1
a
is that the planar structure provides a more precise pattern of the word lines and such precision permits scaling of structures to a smaller size. However, a recognized disadvantage of the planar structure is that there are no surface height variations that can be optically detected for aligning the word line pattern (and various other critical mask patterns) to the bit lines during the fabrication process.
Consequently, a need exists for a fabrication process for fabricating planar structure charge trapping dielectric memory cells that provides for facilitating mask alignment between the various masking steps.
SUMMARY OF THE INVENTION
A first aspect of the present invention is to provide a method of fabricating a planar architecture charge trapping dielectric memory cell array. The method comprises exposing a first photoresist to a first illumination pattern from a first lithography mask to pattern bit line regions in a core region of the wafer and to simultaneously pattern alignment mark regions on the wafer. Such first photoresist may be over a composite charge trapping dielectric layer on the surface of the wafer. The alignment mark

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